LP3910 Datasheet, PDF (51/72 Pages) Texas Instruments – Power Management IC for Hard-Drive-Based Portable Media Players

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Programming (continued)
LP3910
SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015
MSB
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
LSB
R/W
bit0
1
1
0
0
0
0
0
I²C SLAVE address (chip address)
Figure 71. I²C Chip Address
ack from slave
ack from slave
ack from slave
start msb Chip Address lsb w ack msb Register Add lsb ack msb DATA lsb ack stop
SCL
1 2 3 4 5 6 7 8 9 1 2 3 ...
SDA
start
id = K¶60
w ack
addr = K¶00
ack
DGGUHVV K¶$$ GDWD
w = write (I²C_SDA = 0)
r = read (I²C_SDA = 1)
ack = acknowledge (I²C_SDA pulled down by either master or slave)
rs = repeated start
id = LP3910 chip address: 60’h
Figure 72. I²C Write Cycle
ack stop
8.5.1.6 Register Read Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown
Figure 73.
ack from slave
ack from slave repeated start
ack from slave data from slave ack from master
start msb Chip Address lsb w ack msb Register Add lsb ack rs msb Chip Address lsb r ack msb DATA lsb ack stop
SCL
SDA
start
id = K¶60
w ack register addr = K¶10 ack rs
id = K¶60
r ack
GDWD DGGU K¶6A
ack stop
Figure 73. I²C Read Cycle
8.5.1.7 Multi-Byte I²C Command Sequence
The I²C serial interface of the LP3910 device supports random register multi-byte command sequencing: during
a multi-byte write the Master sends the Start command followed by the device address, which is sent only once,
followed by the 8-bit register address, then 8 bits of data, The I²C slave must then accept the next random
register address followed by 8 bits of data and continue this process until the master sends a valid stop
condition.
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