LP3910 Datasheet, PDF (48/72 Pages) Texas Instruments – Power Management IC for Hard-Drive-Based Portable Media Players

LP3910
SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015
Power Down Caused by External Event
t0 t5
t4 t3 t2
t1
ONOFF
32 ms
deglitch
ONSTAT
(To Microprocessor)
32 ms
deglitch
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VLDO1, VLDO2
T1
VBUCK1
T2
VBUCK2
T3
BUCK/BOOST
NRST
T4
T5
POWERACK
(From Microprocessor)
(Bit D4 in PON register and
POWERBACK pin)
5 ms
VREFH
64 ms
5 ms
Figure 67. Power-Down Event Caused by External Event
8.4.2.5.2 Transition From Active to Standby Mode Due to Expiring POWERACK Deadline
With no external charger present when the system processor fails to acknowledge the power-on in time by
setting either the PACK bit (D4) in the PON register or the POWERACK pin before the 128-ms deadline following
the start of the power-up sequencer, then the NRST is immediately de-asserted and after 2 ms all power sources
are disabled before transitioning to Standby Mode. This 2-ms delay allows the microprocessor to receive a clean
reset before the power is de-asserted. A new power-on event is then required to transition back to active mode.
With either external charger present when the system processor fails to acknowledge the power-on in time by
setting either the PACK bit (D4) in the PON register or the POWERACK pin before the 128-ms deadline following
the start of the power-up sequencer, the NRST is immediately de-asserted; after 2 ms all power sources are
disabled before transitioning to charger standby mode.
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