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LP3910 Datasheet, PDF (14/72 Pages) Texas Instruments – Power Management IC for Hard-Drive-Based Portable Media Players
LP3910
SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015
www.ti.com
7.18 Electrical Characteristics: ADC
All limits apply for TJ = 25°C unless otherwise specified.
PARAMETER
TEST CONDITIONS
VREF
INL
DNL
VGP_IN
Reference voltage
Core ADC integral non-linearity
Core ADC differential non-linearity
TJ = 25°C
TJ = 0°C to 125°C
VREF = 1.225(1)
VREF = 1.225(1)
General purpose ADC input
voltage range
VBATT,
RANGE 0
Battery maximum voltage scalar
output
Battery minimum voltage scalar
output
VBATT = 3.5 V
VBATT = 2.6 V
VBATT,
RANGE 1
Battery maximum voltage scalar
output
Battery minimum voltage scalar
output
VBATT = 4.4 V
VREF = 2.6 V
VISENSE ,
RANGE 0
VISENSE,
RANGE 1
ADC1 and
ADC2MIN
ADC1 and
ADC2MAX
tCONV
tWARM
ISENSE maximum voltage scalar
output
ISENSE minimum voltage scalar
output
ISENSE maximum voltage scalar
output
ISENSE minimum voltage scalar
output
ADC1 and ADC2 minimum
voltage scalar output
ADC1 and ADC2 maximum
voltage scalar output
Conversion time(1)
Warm-up time
VISENSE = 0.6463 V
ICHG = 0.605 A,
RSENSE = 4.64 kΩ
VISENSE = 0 V
ICHG = 0 A,
RSENSE = 4.64 kΩ
VISENSE = 1.175 V
ICHG = 1.1 A,
RSENSE = 4.64 kΩ
VISENSE = 0 V
ICHG = 0 A,
RSENSE = 4.64 kΩ
VREFH = 1.225 V
VREFH = 1.225 V
(1) This specification is ensured by design.
MIN
1.22
1.2
–1
–0.5
VREF
2.435
1.217
2.435
1.217
2.373
TYP
1.225
1.225
MAX
1.23
1.23
1
0.5
2 × VREF
2.45
2.465
UNIT
V
V
LSB
LSB
V
V
1.225
1.232
V
2.45
2.465
V
1.225
1.232
V
2.45
2.519
V
1.186
1.225
1.260
V
2.373
2.45
2.519
V
1.186
1.218
2.436
1.225
1.225
2.45
2
1.26
V
1.23
V
2.46
V
5
ms
ms
7.19 I2C Timing Requirements
Unless otherwise noted, VDDIO = 3.6 V and minimum and maximum limits apply for TJ = 0°C to 125°C.(1)
MIN
NOM
FCLK
Clock frequency
tBF
Bus-free time between START and STOP
1.3
tHOLD
Hold time repeated START condition
0.6
tCLK-LP
CLK low period
1.3
tCLK-HP
CLK high period
0.6
tSU
Set-up time repeated START condition
0.6
tDATA-HOLD Data hold time
0
tDATA-SU
Data set-up time
100
tSU
Set-up time for STOP condition
0.6
Maximum pulse width of spikes that must be suppressed by the input filter
tTRANS
of both data and CLK signals
50
TJ = 25°C
(1) These specifications are ensured by design.
MAX
400
UNIT
kHz
µs
µs
µs
µs
µs
µs
ns
µs
µs
14
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