LP3910 Datasheet, PDF (28/72 Pages) Texas Instruments – Power Management IC for Hard-Drive-Based Portable Media Players

LP3910
SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015
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Feature Description (continued)
8.3.1.3 PWM Operation
During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This
allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional
to the input voltage. To eliminate this dependence, feed-forward voltage inversely proportional to the input
voltage is introduced.
8.3.1.4 Internal Synchronous Rectification
While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
8.3.1.5 Current Limiting
A current limit feature allows the buck to protect itself and external components during overload conditions PWM
mode implements cycle-by-cycle current limiting using an internal comparator that trips at 1000 mA (typical).
8.3.1.6 PFM Operation
At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply
current to maintain high efficiency.
The device automatically transitions into PFM mode when either of two conditions occurs for a duration of 32 or
more clock cycles:
The inductor current becomes discontinuous or the peak PMOS switch current drops below the I_MODE level:
V_IN
(Typically I_MODE < 66 mA + _160: )
(1)
During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy
load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output
FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output
voltage. If the output voltage is below the high PFM comparator threshold, the PMOS power switch is turned on.
It remains on until the output voltage exceeds the high PFM threshold or the peak current exceeds the I_PFM level
set for PFM mode. The typical peak current in PFM mode is:
V_IN
I_PFM = 66 mA + _80:
(2)
Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps
to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output
voltage is below the high PFM comparator threshold (see Figure 50), the PMOS switch is again turned on and
the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM
threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output
switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this
sleep mode is less than 30 µA, which allows the part to achieve high efficiencies under extremely light load
conditions. When the output drops below the low PFM threshold, the cycle repeats to restore the output voltage
to approximately 1.6% above the nominal PWM output voltage.
If the load current increases during PFM mode (see Figure 50) causing the output voltage to fall below the ‘low2’
PFM threshold, the device automatically transitions into fixed-frequency PWM mode.
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