LP3910 Datasheet, PDF (10/72 Pages) Texas Instruments – Power Management IC for Hard-Drive-Based Portable Media Players

LP3910
SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015
www.ti.com
7.8 Detection and Timing
Typical limits apply for T_J = 25°C; minimum and maximum limits apply for T_J = 0°C to 125°C, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
I_PROG = 500 mA
10% EOC setting
I_EOC
End-of-charge current
I_PROG = 500 mA
5% EOC setting
40
50
60 mA
20
25
30 mA
V_RESTART
Battery restart charging
voltage
V_TERM = 4.1 V
V_TERM = 4.2 V
V_TERM = 4.38 V
3.82
3.9
3.94
3.94
4
4.06
V
4.14
4.2
4.26
7.9 Output Electrical Characteristics: CHG, STAT
Unless otherwise noted, V_DD = 5 V, V_BATT = 3.6 V. C_BATT = 4.7 µF, C_{CHG_DET} = 10 µF. Typical limits apply for T_J = 25°C;
minimum and maximum limits apply for T_J = 0°C to 125°C, unless otherwise specified.^(1)(2)(3)(4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
V_LED = 2 V
CHSPV Register (02)h bit 5 = 1
4
5
6
(standard)
I_LED
Output high level
V_LED = 2 V
mA
CHSPV Register (02)h bit 5 = 1 (AP
0.75
1
1.25
version only)
V_LED = 2 V
CHSPV Register (02)h bit 5 = 0
(standard)
I_LED
Output high level
V_LED = 2 V
CHSPV Register (02)h bit 5 = 0 (AP
version only)
8
10
12
mA
1.6
2
2.4
I_LEAKAGE
LED_FREQ
Leakage current
Blinking frequency
V_LED = 1.5 V, LED off
0.1
5
µA
0.8
1
1.2
Hz
(1) All voltages are with respect to the potential at the GND pin.
(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
(3) Minimum and maximum limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the
most likely norm.
(4) Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
7.10 Output Electrical Characteristics: NRST, IRQB, ONSTAT
Unless otherwise noted, V_DD = 5 V, V_BATT = 3.6 V, C_BATT = 4.7 µF, C_{CHG_DET} = 10 µF. Minimum and maximum limits apply over
the entire junction temperature range for operation, T_J = 0°C to 125°C.^(1)(2)(3)(4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
V_OL
Output low level
I_OL = 4 mA
I_LEAKAGE
Leakage current
V_DD = 2.5 V, output logic high
–1
0.4
V
1
µA
(1) All voltages are with respect to the potential at the GND pin.
(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
(3) Minimum and maximum limits are specified by design, test, or statistical analysis.
(4) Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
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