DS92LX2121_14 Datasheet, PDF (5/43 Pages) Texas Instruments – 10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserializer

DS92LX2121, DS92LX2122
www.ti.com
SNLS330J – MAY 2010 – REVISED JANUARY 2014
DS92LX2122 Deserializer PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
ROUT[20:0]
5, 6, 8, 9, 10,
11, 12, 13, 14,
15, 16, 18, 19,
21, 22, 23, 24,
25, 26, 27, 28
Outputs, LVCMOS Parallel data outputs.
PCLK
Pixel Clock Output Pin.
4
Output, LVCMOS Strobe edge set by RFB configuration. In SLEEP, outputs are controlled by the
OSS_SEL.
General Purpose Input (GPI)
GPI[3:0]
30, 31, 32, 33
Input, Digital
SERIAL CONTROL BUS - I²C COMPATIBLE
General-purpose pins individually configured as inputs; which are used to
control and respond to various commands.
SCL
SDA
2
Input/Output, Open Clock line for the serial control bus communication
Drain
SCL requires an external pull-up resistor to V_DDIO.
1
Input/Output, Open Data line for serial control bus communication
Drain
SDA requires an external pull-up resistor to V_DDIO.
I²C Mode Select
M/S = L, Master; device generates and drives the SCL clock line. Device is
M/S
47
Input, LVCMOS w/ connected to slave peripheral on teh bus.
pull up
M/S = H, Slave (default); device accepts SCL clock input and is attached to an
I²C controller master on the bus. Slave mode does not generate the SCL clock,
but uses the clock generated by teh Master for teh data transfer.
Continuous Address Decoder
CAD
48
Input, analog
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID address
(see Serial Control Bus Connection)
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB
35
Input, LVCMOS w/ ^{PDB = H, Receiver is enabled and is ON.}
pull down
PDB = L, Receiver is in Sleep (Power down mode). When the Receiver is in the
SLEEP state, the LVCMOS Outputs are in TRI-STATE, the PLL is shutdown
and IDD is minimized.
LOCK Status Output Pin.
LOCK
34
Output, LVCMOS ^{LOCK = H, PLL is Locked, outputs are active}
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL. May be used as Link Status.
Reserved.
RES
38, 39, 43, 46
-
Pin 43: Leave pin open.
Pin 46: This pin MUST be tied LOW.
Pins 38, 39: Route to test point as differential pair or leave open if unused.
BIST MODE
BISTEN
BIST Enable Pin.
44
Input, LVCMOS w/
pull down
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
PASS Output Pin for BIST mode.
PASS
PASS = H, ERROR FREE Transmission
37
Output, LVCMOS
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
Channel Link III INTERFACE
RIN+
41
Input/Output, CML
Non-inverting differential input, back channel output. The interconnect must be
AC coupled with a 0.1μF capacitor.
RIN-
42
Input/Output, CML
Inverting differential input, back channel output. The interconnect must be AC
coupled with a 0.1 μF capacitor.
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