DS92LX2121_14 Datasheet, PDF (4/43 Pages) Texas Instruments – 10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserializer

DS92LX2121, DS92LX2122
SNLS330J – MAY 2010 – REVISED JANUARY 2014
www.ti.com
DS92LX2121 Serializer PIN DESCRIPTIONS (continued)
Pin Name
Pin No.
CONTROL AND CONFIGURATION
I/O, Type
PDB
13
Input, LVCMOS w/
pull down
RES
10, 11
Channel Link III INTERFACE
DOUT+
17
DOUT-
16
Power and Ground
VDDPLL
14
VDDT
15
VDDCML
18
VDDD
34
VDDIO
31
VSS
DAP
Input, LVCMOS w/
pull down
Input/Output, CML
Input/Output, CML
Power, Analog
Power, Analog
Power, Analog
Power, Digital
Power, Digital
Ground, DAP
Description
Power down Mode Input Pin.
PDB = H, Transmitter is enabled and is ON.
PDB = L, Transmitter is in Sleep (Power Down). When the transmitter is in the
SLEEP state, the PLL is shutdown, and IDD is minimized.
Reserved. This pin MUST be tied LOW.
Non-inverting differential output, back-channel input.
Inverting differential output, back-channel input.
PLL Power, 1.8V ±5%
Tx Analog Power, 1.8V ±5%
LVDS & BC Dr Power, 1.8V ±5%
Digital Power, 1.8V ±5%
Power for input stage, The single-ended inputs are powered from V_DDIO.
DAP must be grounded. Connect to the ground plane (GND) with at least 16
vias.
DS92LX2122 Pin Diagram
Top View
PASS 37
RES 38
RES 39
V_DDCML 40
RIN+ 41
RIN- 42
RES 43
BISTEN 44
V_DDPLL 45
RES 46
M/S 47
CAD 48
DAP = GND
DS92LX2122
(Top View)
24 ROUT[4]
23 ROUT[5]
22 ROUT[6]
21 ROUT[7]
20 V_DDOR2
19 ROUT[8]
18 ROUT[9]
17 V_DDD
16 ROUT[10]
15 ROUT[11]
14 ROUT[12]
13 ROUT[13]
Figure 4. Deserializer - DS92LX2122
48-Pin WQFN (RHS Package)
4
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX2121 DS92LX2122