DS92LX2121_14 Datasheet, PDF (11/43 Pages) Texas Instruments – 10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserializer

DS92LX2121, DS92LX2122
www.ti.com
SNLS330J – MAY 2010 – REVISED JANUARY 2014
Serializer Electrical Characteristics Deserializer Switching Characteristics^(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
t_CLH
t_CHL
LVCMOS Low-to-High Transition
Time
LVCMOS High-to-Low Transition
Time
V_DDIO: 1.71 V to 1.89 V
or 3.0 V to 3.6 V,
CL = 8pF (lumped load)
Default Registers
(Figure 17) ⁽⁴⁾
Deserializer Data
Outputs
1.6
1.6
t_ROS
t_ROH
ROUT Setup Data to PCLK
ROUT Hold Data to PCLK
V_DDIO: 1.71 V to 1.89 V
or 3.0 V to 3.6 V, CL =
8pF (lumped load)
Default Registers
Deserializer Data
Outputs
0.38
0.38T
t_DD
t_DDLT
t_RJIT
t_DCJ
Deserializer Delay
Deserializer Data Lock Time
Receiver Input Jitter Tolerance
Deserializer Clock Jitter
Default Registers
Register 0x03h b[0]
(RRFB = 1)
Figure 18
(5)
PCLK
SSCG[3:0] = OFF
(8) (9)
10 MHz - 50 MHz
10 MHz - 50 MHz
(6) (7)_{50 MHz}
10 MHz
50 MHz
4.571T +
8
Typ
2.4
2.4
0.5
0.5T
4.571T +
12
0.53
300
120
Max
3.3
3.3
4.571T
+ 16
10
550
250
Units
ns
T
ns
ms
UI
ps
t_DPJ
Deserializer Period Jitter
PCLK
SSCG[3:0] = OFF
(10) (9)
10 MHz
50 MHz
425
600
320
480
ps
t_DCCJ
Deserializer Cycle-to-Cycle Clock
Jitter
PCLK
SSCG[3:0] = OFF
(11) (9)
10 MHz
50 MHz
320
500
300
500
ps
f_DEV
f_MOD
Spread Spectrum Clocking
Deviation Frequency
Spread Spectrum Clocking
Modulation Frequency
LVCMOS Output Bus
SSC[3:0] = ON
Figure 20
20 MHz - 50 MHz
20 MHz - 50 MHz
±0.5% to
±2.0%
%
9 kHz to
66 kHz
kHz
(5) t_PLD and t_DDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK.
(6) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
(7) t_RJIT max (0.61UI) is limited by instrumentation and actual t_RJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI.
(8) t_DCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
(9) Specification is ensured by characterization and is not tested in production.
(10) t_DPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
(11) t_DCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
Bi-Directional Control Bus AC Timing Specifications (SCL, SDA) - I²C Compliant (Figure 5)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
RECOMMENDED INPUT TIMING REQUIREMENTS⁽¹⁾
Conditions
Min
Typ
Max
Units
f_SCL
f_LOW
f_HIGH
t_HD:STA
SCL Clock Frequency
SCL Low Period
SCL High Period
Hold time for a start or a repeated start
condition
f_SCL = 100 kHz
>0
100
kHz
4.7
µs
4.0
µs
4.0
µs
t_SU:STA
Set Up time for a start or a repeated
start condition
4.7
µs
t_HD:DAT
t_SU:DAT
t_SU:STO
t_r
t_f
C_b
Data Hold Time
Data Set Up Time
Set Up Time for STOP Condition,
SCL & SDA Rise Time
SCL & SDA Fall Time
Capacitive load for bus
0
3.45
µs
250
ns
4.0
µs
1000
ns
300
ns
400
pF
(1) Recommended Input Timing Requirements are input specifications and not tested in production.
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