DS92LX2121_14 Datasheet, PDF (28/43 Pages) Texas Instruments – 10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserializer

DS92LX2121, DS92LX2122
SNLS330J – MAY 2010 – REVISED JANUARY 2014
www.ti.com
Wait 10 ms for Deserializer to acquire lock and then monitor the LOCK pin transition from LOW to HIGH. At this
point, AT SPEED BIST is operational and the BIST process has begun. The Serializer will start transfer of an
internally generated PRBS data pattern through the high speed serial link. This pattern traverses across the
interconnecting link to the Deserializer. Check the status of the PASS pin; a HIGH indicates a pass, a LOW
indicates a fail. A fail will stay LOW for ½ a clock cycle. If two or more bits fail in a row the PASS pin will toggle ½
clock cycle HIGH and ½ clock cycle low. The user can use the PASS pin to count the number of fails on the high
speed link. In addition, there is a defined SER and DES register that will keep track of the accumulated error
count. The Serializer DS92LX2121 GPIO[0] pin will be assigned as a PASS flag error indicator for the back-
channel link.
Recovered
Pixel Clock
BISTEN
Case 1: No bit errors
Recovered
Pixel Data
PASS
Previous
³&5&´6WDWH
³&5&´6WDWH
Case 2: Bit error(s)
Recovered
Pixel Data
B
BB
B
PASS
Previous
³&5&´6WDWH
E
EE
E
Case 3: Bit error(s) AFTER BIST Duration
Recovered
Pixel Data
PASS
Previous
³&5&´6WDWH
³&5&´6WDWH
B
³&5&´6WDWH
B = Bad Pixel
PE = Payload Error
BIST Duration
(when BISTEN=H)
Figure 31. BIST Timing Diagram
CRC Status
(when BISTEN=L)
Step 3: Stop at SPEED BIST by turning off BIST mode in the Deserializer to determine Pass/Fail.
To end BIST, the system must pull BISTEN pin of the Deserializer LOW. The BIST duration is fully defined by
the BISTEN width and thus the Bit Error Rate is determined by how long the system holds BISTEN HIGH.
BIST Duration (s)
1 Pixel period (ns) x Total Bits
= BIST Duration (s) x
f_pixel (MHz)
Pixel
x Total Pixels Transmitted = Total Bits Transmitted
Bit (Pixel) Error Rate
(for passing BIST)
=
[Total Bits Transmitted] ^-1
= [Total Bits Transmitted x Bits/Pixel] ^-1
Figure 32. BIST BER Calculation
For instance, if BISTEN is held HIGH for 1 second and the PCLK is running at 43 MHz with 16 bpp, then the Bit
Error Rate is no better than 1.46E-9.
Step 4: Place system in Normal Operating Mode by disabling BIST at the Serializer.
Once Step 3 is complete, AT SPEED BIST is over and the Deserializer is out of BIST mode. To fully return to
Normal mode, apply Normal input data into the Serializer.
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