DS92LX2121_14 Datasheet, PDF (24/43 Pages) Texas Instruments – 10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserializer

DS92LX2121, DS92LX2122
SNLS330J – MAY 2010 – REVISED JANUARY 2014
HOST
SCL
SDA
1.8V
V_DDIO
4.7k
4.7k
10k
CAD
R_CAD
SER
or
SCL _DES
SDA
www.ti.com
To other
Devices
Figure 28. Serial Control Bus Connection
SLAVE CLOCK STRETCHING
In order to communicate and synchronize with remote devices on the I²C bus through the bi-directional control
channel, slave clock stretching must be supported by the I²C master controller/host device. The chipset utilizes
bus clock stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line
low on the 9th clock of every I²C data transfer (before the ACK signal). The slave device will not control the clock
and only stretches it until the remote peripheral has responded; which is typically in the order of 12 μs (typical).
CAD PIN ADDRESS DECODER
The CAD pin is used to decode and set the physical slave address of the Serializer/Deserializer (I²C only) to
allow up to six devices on the bus using only a single pin. The pin sets one of six possible addresses for each
Serializer/Deserializer device. The pin must be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor and a
pull down resistor (RID) of the recommended value to set the physical device address. The recommended
maximum resistor tolerance is 0.1% worst case (0.2% total tolerance).
Resistor RID kΩ
0
GND
2.0k
4.7k
8.2k
12.1k
39.0k
Table 3. DS92LX2121 RID Resistor Values
CAD Values - DS92LX2121 Ser
Address 7'b
Address 8'b 0 appended (WRITE)
7b' 101 1000 (h'58)
8b' 1011 0000 (h'B0)
7b' 101 1001 (h'59)
7b' 101 1010 (h'5A)
7b' 101 1011 (h'5B)
7b' 101 1100 (h'5C)
7b' 101 1110 (h'5E)
8b' 1011 0010 (h'B2)
8b' 1011 0100 (h'B4)
8b' 1011 0110 (h'B6)
8b' 1011 1000 (h'B8)
8b' 1011 1100 (h'BC)
Resistor RID kΩ
0
GND
2.0k
4.7k
8.2k
12.1k
39.0k
Table 4. DS92LX2122 RID Resistor Values
CAD Values - DS92LX2122 Des
Address 7'b
Address 8'b 0 appended (WRITE)
7b' 110 0000 (h'60)
8b' 1100 0000 (h'C0)
7b' 110 0001 (h'61)
7b' 110 0010 (h'62)
7b' 110 0011 (h'63)
7b' 110 0100 (h'64)
7b' 110 0110 (h'66)
8b' 1100 0010 (h'C2)
8b' 1100 0100 (h'C4)
8b' 1101 0110 (h'C6)
8b' 1101 1000 (h'C8)
8b' 1100 1100 (h'CC)
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