DS90UA102-Q1_14 Datasheet, PDF (5/47 Pages) Texas Instruments – Multi-Channel Digital Audio Link

DS90UA102-Q1
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SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013
Pin Name
Pin #
I/O, Type
Description
OEN
5
Input, LVCMOS Output enable. Refer to Table 5.
w/ pull down
BISTEN
6
Input, LVCMOS BIST enable pin.
w/ pull down BISTEN = H, BIST mode is enabled.
BISTEN = L, BIST mode is disabled.
PDB
IDx
30
Input, LVCMOS Power down mode input pin.
w/ pull down PDB = H device is enabled and is ON.
PDB = L, device is powered down.
When the device is in the powered down state, the PLL is shutdown, IDD is minimized,
and control registers are RESET.
35
Input, Analog Device I²C address select.
The IDx pin on the Deserializer is used to assign its I²C device address. See Table 2.
DO NOT FLOAT.
Serial Interface
RIN+
41
Input, LVDS True serial interface input.
The interconnection must be AC-coupled to this pin with a 0.1 µF capacitor.
RIN-
42
Input, LVDS Inverting serial interface input.
The interconnection must be AC-coupled to this pin with a 0.1 µF capacitor.
CMLOUTP
38
Output, LVDS True CML output.
Monitor point for equalized input signal.
CMLOUTN
39
Output, LVDS Inverting CML output.
Monitor point for equalized input signal.
Status
PASS
47
Output, LVCMOS PASS status output pin.
PASS = H: Error-free transmission (applies to BIST and normal operation).
PASS = L: One or more parity errors occurred in the received payload. In normal and
BIST mode, PASS pin toggles low momentarily for each parity error. In BIST mode only,
PASS pin also toggles low momentarily at the end of the BIST if at least one error
occurred during the test.
Leave open if unused. Otherwise, route to a test point/pad (recommended).
LOCK
48
Output, LVCMOS LOCK status output pin.
LOCK = H: PLL is locked; Deserializer outputs are active.
LOCK = L: PLL is unlocked; Deserializer outputs are not valid with respect to Serializer
inputs.
Leave open if unused. Otherwise, route to a test point/pad (recommended).
Power and Ground
VDDR
3, 36
Power
1.8V (±5%) analog core power.
VDDIO
7, 20, 29
Power
LVCMOS I/O power. 1.8V (±5%) or 3.3V (±10%).
VDDD
17
Power
1.8V (±5%) digital power.
VDDCML
31, 40
Power
1.8V (±5%) CML receiver and Bidirectional Control Channel power.
VDDPLL
45
Power
1.8V (±5%) PLL power.
GND
DAP
Ground
DAP is the large metal contact located at the bottom center of the LLP package.
Connect to the GND plane with at least 9 vias.
Other
RES0
34, 37, 43, 44,
46
Reserved
Reserved.
Tie to GND.
RES1
32, 33
Reserved
Reserved.
Leave floating.
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