DS90UA102-Q1_14 Datasheet, PDF (28/47 Pages) Texas Instruments – Multi-Channel Digital Audio Link

DS90UA102-Q1
SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013
LRCK
RIGHT Channel Data
LEFT Channel Data
www.ti.com
BCK
DIN 0
210
MSB
LSB
MSB
Figure 16. Right-Justified Format
210
LSB
TDM Format
There are no well defined rules for TDM format and it can be implemented in large number of ways depending
upon the word length, bit clock, number of channels to be multiplexed, etc. For example, let’s assume that word
clock signal (LRCK) period = 256 * bit clock (BCK) time period. In this case, we can multiplex 4 channels with
maximum word length of 64 bits each, or 8 channels with maximum word length of 32 bits each. Figure 17
illustrates the multiplexing of 8 channels with 24 bit word length, in a format similar to I²S.
Pulse width of LRCK can be used to define a clock period for BCK or to define a slot period, i.e., the period for
which individual channel can be active on the shared data line.
If the number of audio channels is more than 8, DS90UA101-Q1/DS90UA102-Q1 can easily support multiplexed
data with additional devices to multiplex and de-multiplex the data. The number of channels multiplexed on each
data line must be selected as a power of 2, that is, 2/ 4/ 8.
LRCK
t1/fS (256 BCKs at Single Rate, 128 BCKs at Dual Rate)t
BCK
I²S Mode
DIN1
(Single)
Ch 1
t32 BCKst
23 22 0
Ch 2
t32 BCKst
23 22 0
Ch 3
t32 BCKst
23 22 0
Ch 4
t32 BCKst
23 22 0
Ch 5
t32 BCKst
23 22 0
Ch 6
t32 BCKst
23 22 0
Ch 7
t32 BCKst
23 22 0
Ch 8
t32 BCKst
23 22 0
23 22
Figure 17. TDM Format
Error Detection
The chipset provides error detection operations for validating data integrity in long distance transmission and
reception. The data error detection function offers users flexibility and usability of performing bit-by-bit data
transmission error checking. The error detection operating modes support data validation of the following signals:
• Bidirectional Control Channel data across the serial link
• Parallel audio/sync data across the serial link
The chipset provides 1 parity bit on the forward channel and 4 CRC bits on the back channel for error detection
purposes. The DS90UA101-Q1/DS90UA102-Q1 chipset checks the forward and back channel serial links for
errors and stores the number of detected errors in two 8-bit registers in the Serializer and the Deserializer,
respectively.
28
Submit Documentation Feedback
Product Folder Links: DS90UA102-Q1
Copyright © 2013, Texas Instruments Incorporated