DS90UA102-Q1_14 Datasheet, PDF (10/47 Pages) Texas Instruments – Multi-Channel Digital Audio Link

DS90UA102-Q1
SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013
ELECTRICAL CHARACTERISTICS:
Deserializer Switching Characteristics
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Over recommended operating supply and temperature ranges unless otherwise specified.^{(1) (2) (3)}
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
t_RCP
Receiver Output
STP Cable
Clock Period
Coaxial Cable
SCK (Figure 9)
20
T
20
T
t_PDC
SCK Duty Cycle
SCK
t_CLH
LVCMOS Low-to- V_DDIO: 1.71V to 1.89V or 3.0V SCK
High Transition Time to 3.6V,
t_CHL
LVCMOS High-to-
Low Transition Time
C_L = 8 pF (lumped load)
Default Registers
(Figure 7),⁽⁴⁾
40
50
1.3
2
1.3
2
t_CLH
LVCMOS Low-to- V_DDIO: 1.71V to 1.89V or 3.0V DOUT[7:0], GPO[3:0],
High Transition Time to 3.6V,
BCK, LRCK
1
2.5
t_CHL
LVCMOS High-to-
Low Transition Time
C_L = 8 pF (lumped load)
Default Registers
(Figure 7),⁽⁴⁾
1
2.5
t_ROS
Setup Data to SCK V_DDIO: 1.71V to 1.89V or 3.0V DOUT[7:0], GPO[3:0],
0.38
0.5
t_ROH
Hold Data to SCK
to 3.6V,
C_L = 8 pF (lumped load)
BCK, LRCK
0.38
0.5
Default Registers (Figure 9)
Default Registers
t_DD
Deserializer Delay Register 0x03h b[0] (RRFB = 1)
109
(Figure 8),⁽⁴⁾
t_DDLT
Deserializer Data
Lock Time
With Adaptive Equalization
(Figure 6)
15
t_RCJ
Receiver Clock Jitter SCK⁽⁴⁾
SCK = 50 MHz
22
t_DPJ
Deserializer Period SCK ⁽⁵⁾⁽⁴⁾
Jitter
SCK = 50 MHz
180
t_DCCJ
Deserializer Cycle- SCK ⁽⁶⁾⁽⁴⁾
to-Cycle Clock Jitter
SCK = 50 MHz
460
Max
Units
100
ns
40
60
%
2.8
ns
2.8
4
ns
4
T
112
T
22
ms
35
ps
330
ps
730
ps
(1) The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not
verified.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except V_OD, ΔV_OD, V_TH and V_TL which are differential voltages.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, T_A = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not verified .
(4) Specification is verified by characterization and is not tested in production.
(5) t_DPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
(6) t_DCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
10
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