DS90UA102-Q1_14 Datasheet, PDF (16/47 Pages) Texas Instruments – Multi-Channel Digital Audio Link

DS90UA102-Q1
SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013
DS90UA102-Q1 REGISTER INFORMATION
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The table below contains information on the DS90UA102-Q1 control registers. These registers are accessible
locally via the I²C control interface, or remotely via the Bidirectional Control Channel. Addresses not listed are
reserved. Fields listed as reserved should not be changed from the listed default value.
Addr
(Hex)
Name
Bits
Field
R/W
Default (Hex)
Description
0x00
I²C Device ID
7:1 DEVICE ID
0 DES ID SEL
RW
7-bit address of Deserializer.
0x60'h (0110_000X'b) default.
0xC0
RW
0: Deserializer DEVICE ID is from IDx.
1: Register I²C DEVICE ID overrides IDx.
0x01
Reset
7:6 RSVD
5 ANAPWDN
4:2 RSVD
0x04
Reserved.
This register can be set only through local I²C
access.
RW
1: Analog power-down : Powers down the
analog block in the Deserializer.
0: Analog power-up: Powers up the analog
block in the Deserializer.
Reserved.
1 Digital Reset 1
RW
1: Resets the digital block except for register
values. This bit is self-clearing.
0: Normal operation.
0 Digital Reset 0
RW
1: Resets the entire digital block including all
register values. This bit is self-clearing.
0: Normal operation.
7:6 RSVD
0x00
Reserved.
0x02
General
Configuration 0
5 Auto-Clock
RW
1: Output SCK when LOCKED or internal
oscillator clock when not LOCKED.
0: Output SCK when LOCKED only.
4:0 RSVD
Reserved.
16
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