DS90UA102-Q1_14 Datasheet, PDF (13/47 Pages) Texas Instruments – Multi-Channel Digital Audio Link

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TIMING AND CIRCUIT DIAGRAMS
DS90UA102-Q1
SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013
SDA
t_f
SCL
START
t_LOW
t_r
t_f
t_HD;STA
t_BUF
t_r
t_HD;STA
t_HD;DAT
t_HIGH
t_SU;DAT
t_SU;STA
t_SU;STO
REPEATED
START
Figure 4. Bi-directional Control Bus Timing
STOP START
Single-Ended
DOUT-
VOD
DOUT+
V_OD+
V_OD-
§ V_OS
Differential
V_OD+
(DOUT+) - (DOUT-)
0V
V_OD-
Figure 5. Differential Vswing Diagram
PDB ^VDDIO/2
RIN±
t_DDLT
LOCK TRI-STATE
VDDIO/2
Figure 6. Deserializer Data Lock Time
Deserializer
8 pF
lumped
80%
20%
80%
20%
t_CLH
t_CHL
Figure 7. Deserializer LVCMOS Output Load and Transition Times
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