DS90UA102-Q1_14 Datasheet, PDF (17/47 Pages) Texas Instruments – Multi-Channel Digital Audio Link

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Addr
(Hex)
0x03
Name
Bits
Field
R/W
7
RX Parity Checker
Enable
RW
6
TX CRC Checker
Enable
RW
5 V_DDIO Control
RW
General
Configuration 1
4 V_DDIO Mode
RW
I²C Pass-Through
3
RW
2
I²C Remote Write
Auto Acknowledge
RW
1 Parity Error Reset
RW
0 RRFB
RW
0x04
EQ Feature
Control
7:0 EQ Level
RW
DS90UA102-Q1
SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013
Default (Hex)
0xE9
0x00
Description
Forward channel Parity Checker enable.
1: Enable.
0: Disable.
Back channel CRC Generator enable.
1: Enable.
0: Disable.
Auto voltage control.
1: Enable (auto-detect mode).
0: Disable.
V_DDIO voltage set.
1: Sets V_DDIO mode to 3.3V.
0: Sets V_DDIO mode to 1.8V.
I²C pass-through mode.
1: Pass-through enabled. Refer to I²C Pass-
Through and Multiple Device Addressing.
0: Pass-through disabled.
Automatically acknowledge I²C remote writes.
This mode should only be used when the
system is LOCKED.
1: Enable: When enabled, I²C writes to the
Serializer (or any remote I²C slave, if I²C Pass
All is enabled) are immediately acknowledged
without waiting for the Serializer to
acknowledge the write. The accesses are then
remapped to address specified in 0x06.
0: Disable.
Clear parity error counters. This bit is self-
clearing.
1: Clear parity error counters.
0: Normal operation.
SCK clock edge select.
1: Parallel interface data is strobed on the rising
clock edge.
0: Parallel interface data is strobed on the
falling clock edge.
Equalization gain: When AEQ bypass is
enabled EQ setting is provided by this register.
0x00 = ~0.0 dB.
0x01 = ~4.5 dB.
0x03 = ~6.5 dB.
0x07 = ~7.5 dB.
0x0F = ~8.0 dB.
0x1F = ~11.0 dB.
0x3F = ~12.5 dB.
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: DS90UA102-Q1
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