CC3220MOD Datasheet, PDF (47/82 Pages) Texas Instruments – SimpleLink Wi-Fi CERTIFIED Wireless Module Solution

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CC3220MOD
SWRS206 – MARCH 2017
Figure 5-15 shows the ADC clock timing diagram.
Internal Ch
Repeats Every 16 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
ADC CLOCK
= 10 MHz
Sampling
4 cycles
SAR Conversion
16 cycles
EXT CHANNEL 0
Sampling
4 cycles
SAR Conversion
16 cycles
INTERNAL CHANNEL
Sampling
4 cycles
SAR Conversion
16 cycles
EXT CHANNEL 1
Figure 5-15. ADC Clock Timing Diagram
Sampling
4 cycles
SAR Conversion
16 cycles
INTERNAL CHANNEL
5.14.3.7 Camera Parallel Port
The fast camera parallel port interfaces with a variety of external image sensors, stores the image data in
a FIFO, and generates DMA requests. The camera parallel port supports 8 bits.
Figure 5-16 shows the timing diagram for the camera parallel port.
13
12
14
pCLK
16
17
pVS, pHS
pDATA
Figure 5-16. Camera Parallel Port Timing Diagram
Table 5-13 lists the timing parameters for the camera parallel port.
Table 5-13. Camera Parallel Port Timing Parameters
PARAMETER NUMBER
I2
I3
I4
I6
I7
pCLK
T_clk
t_LP
t_HT
t_IS
t_IH
MIN
Clock frequency
Clock period
Clock low period
Clock high period
RX data setup time
RX data hold time
MAX
2
1/pCLK
T_clk/2
T_clk/2
2
2
UNIT
MHz
ns
ns
ns
ns
ns
5.14.3.8 UART
The CC3220MODx device includes two UARTs with the following features:
• Programmable baud-rate generator allowing speeds up to 3 Mbps
• Separate 16-bit × 8-bit TX and RX FIFOs to reduce CPU interrupt service loading
• Programmable FIFO length, including a 1-byte-deep operation providing conventional double-buffered
interface
• FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
• Standard asynchronous communication bits for start, stop, and parity
• Generation and detection of line-breaks
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Specifications
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