CC3220MOD Datasheet, PDF (45/82 Pages) Texas Instruments – SimpleLink Wi-Fi CERTIFIED Wireless Module Solution

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CC3220MOD
SWRS206 – MARCH 2017
Table 5-10 lists the I²C timing parameters.
Table 5-10. I²C Timing Parameters⁽¹⁾
PARAMETER
NUMBER
MIN
MAX
UNIT
I2
t_LP
I3
t_SRT
Clock low period
SCL/SDA rise time
See ⁽²⁾
System clock
See ⁽³⁾
ns
I4
t_DH
Data hold time
NA
I5
t_SFT
I6
t_HT
SCL/SDA fall time
Clock high time
3
See ⁽²⁾
ns
System clock
I7
t_DS
Data setup time
tLP/2
System clock
I8
t_SCSR
Start condition setup time
36
System clock
I9
t_SCS
Stop condition setup time
24
System clock
(1) All timing is with 6-mA drive and 20-pF load.
(2) This value depends on the value programmed in the clock period register of I²C. Maximum output frequency is the result of the minimal
value programmed in this register.
(3) Because I²C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of external pullup. Rise time depends on
the value of the external signal capacitance and external pullup register.
5.14.3.5 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and
boundary scan architecture for digital integrated circuits and provides a standardized serial interface to
control the associated test logic. For detailed information on the operation of the JTAG port and TAP
controller, see the IEEE Standard 1149.1,Test Access Port and Boundary-Scan Architecture.
Figure 5-14 shows the JTAG timing diagram.
J2
J3
J4
TCK
TMS
J7
J8
TMS Input Valid
J7
J8
TMS Input Valid
TDI
J11
TDO
J9
J10
TDI Input Valid
J1
TDO Output Valid
J9
J10
TDI Input Valid
TDO Output Valid
Figure 5-14. JTAG Timing Diagram
SWAS031-069
Table 5-11 lists the JTAG timing parameters.
PARAMETER
NUMBER
J1
J2
J3
J4
J7
J8
f_TCK
t_TCK
t_CL
t_CH
t_{TMS_SU}
t_{TMS_HO}
Table 5-11. JTAG Timing Parameters
Clock frequency
Clock period
Clock low period
Clock high period
TMS setup time
TMS hold time
MIN
MAX UNIT
15 MHz
1 / f_TCK
ns
t_TCK / 2
ns
t_TCK / 2
ns
1
ns
16
ns
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