THS8083 Datasheet, PDF (44/61 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL

4.4 Timing Diagram – 48-Bit Parallel Mode
This mode allows a double-pixel width output interface with no time offset between buses A and B. The DATACLK1
output is at half of the sampling clock frequency.
ADCCLK1
pix 01 pix 02
DATACLK
tsu(OUT)
th(OUT)
CH1_OUTA[7..0]
CH1_OUTB[7..0]
CH2_OUTA[7..0]
CH2_OUTB[7..0]
CH3_OUTA[7..0]
CH3_OUTB[7..0]
HS
DHS
(DHS_POL = 0
Assumed-Inverted
Polarity Otherwise)
OE
Last Samples From Previous Line 01
03
05
Last Samples From Previous Line
02
04
Last Samples From Previous Line 01
03
05
Last Samples From Previous Line
02
04
Last Samples From Previous Line 01
03
05
tdlh(OE)
Last Samples From Previous Line
02
tdhl(OE)
7 ADCCLK2 Cycles Latency
04
7 ADCCLK2
Cycles Latency
tsu(DHS)
th(DHS)
<DHS_MODE> = 1 –> Width
Equal to Width of HS Input
<DHS_MODE> = 0 –> DHS
Width is 1 ADCCLK2 Period
4–4