THS8083 Datasheet, PDF (37/61 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL

3.2.32 Register Name: CH1_CLP
MSB
CH1_CLP7
CH1_CLP6
CH1_CLP5
CH1_CLP4
CH1_CLP[7..0]
Programmable clamp value for Channel 1
Default: 0x80 = 128 (mid-range)
CH1_CLP3
CH1_CLP2
Subaddress: 25 (R/W)
CH1_CLP1
LSB
CH1_CLP0
3.2.33 Register Name: CH1_COARSE
Subaddress: 26 (R/W)
MSB
X
LSB
X
CH1_COARSE5 CH1_COARSE4 CH1_COARSE3 CH1_COARSE2 CH1_COARSE1 CH1_COARSE0
CH1_COARSE[5..0]
Coarse PGA value for Channel 1
Default: 0x20 = 32 (mid-range)
3.2.34 Register Name: CH1_FINE
MSB
X
X
X
CH1_FINE4
CH1_FINE[4..0]
Fine PGA value for Channel 1
Default: 0x10 = 16 (mid-range)
CH1_FINE3
CH1_FINE2
Subaddress: 27 (R/W)
CH1_FINE1
LSB
CH1_FINE0
3.2.35 Register Name: CH2_CLP
MSB
CH2_CLP7
CH2_CLP6 CH2_CLP5 CH2_CLP4
CH2_CLP[7..0]
Programmable clamp value for Channel 2
Default: 0x80 = 128 (mid-range)
CH2_CLP3
CH2_CLP2
Subaddress: 28 (R/W)
CH2_CLP1
LSB
CH2_CLP0
3.2.36 Register Name: CH2_COARSE
Subaddress: 29 (R/W)
MSB
X
LSB
X
CH2_COARSE5 CH2_COARSE4 CH2_COARSE3 CH2_COARSE2 CH2_COARSE1 CH2_COARSE0
CH2_COARSE[5..0]
Coarse PGA value for Channel 2
Default: 0x20 = 32 (mid-range)
3.2.37 Register Name: CH2_FINE
MSB
X
X
X
CH2_FINE4
CH2_FINE[4..0]
Fine PGA value for Channel 2
Default: 0x10 = 16 (mid-range)
CH2_FINE3
CH2_FINE2
Subaddress: 2A (R/W)
CH2_FINE1
LSB
CH2_FINE0
3–13