THS8083 Datasheet, PDF (21/61 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL

DIGITAL PLL
PFD_FREEZE
VCOCLK
DTO_DIS ^{(From Analog PLL)}
HS_POL HS_MS
1
1
HS
POL
Noise
Gate
8
HS_WIDTH
LD_THRESH
DISABLE_
PFD
1
1
SELCLK
3
MUX
Compensated in Output
Formatter for Pipeline
Data Delay. Then output
on Terminal DHS With
Polarity Determined by
<DHS_POL>.
1
DHS_MODE
DIV2
1
Phase-
Frequency
Detector
PROG.
LOOP
FILTER
DTO DIV
3P ₃
33
GAIN_N GAIN_P
NOM_INC
Programmable
Divider
Lock
8
Detection
Hysteresis
12
TERM_CNT
Phase PLLCLK
Selector
MUX
D
I
V
I
N
2V
5
PHASESEL
1
SEL_ADCCLK
1
INV2
to ADC
D
I
I
N
V
V
2
ADCCLK2
ADCCLK1
(see NOTE)
DTOCLK3
1
DIV3
1
INV3
LOCK
NOTE: ADCCLK1 is used by the output formatter to generate the DATACLK1 output.
EXT_ADCCLK
Figure 2–6. Digital PLL
The device provides three clock outputs. One of these output signals, DATACLK1, is derived from the ADC clock
output. It is actually equal to the sampling clock but compensated in phase so that its rising edge always corresponds
to the center valid region of the output data. Output data timing (setup/hold) is specified with respect to this rising edge.
Therefore, DATACLK1 is typically used for clocking the THS8083’s output data. The frequency of DATACLK1 will be
either equal or 1/2 of the sampling clock, depending on the operation mode of the output formatter. When the
THS8083 is clocked with an external sampling clock, this external clock is used as the source to generate DATACLK1
in the output formatter.
The second clock output, ADCCLK2, is equal to the ADC sampling clock but can optionally be divided by 2 and
inverted.
Finally, the third clock output, DTOCLK3, is always derived from the PLL output clock, irrespective of the use of an
external sampling clock on EXT_ADCCLK. So, when operating with an external sampling clock, the DTOCLK3 output
can be used to generate a second, possibly asynchronous, clock signal in either open loop operation or in closed loop
locked to a reference HS input. Also, DTOCLK3 can be optionally divided by 2 and inverted.
The divide and invert functions are implemented to enable a master/slave operation of two parts in case higher
sampling speeds than 80 MSPS are required. In this case the master will use its PLL to generate a line-locked clock,
of which the inverse will be used as an external sampling clock by the second slave device.
2–7