THS8083 Datasheet, PDF (20/61 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL

The PFD also provides a LOCK output on a dedicated output terminal. This output has a programmable hysteresis
(LD_THRES register value). Details are explained in the section that describes the register map of this device. The
LOCK output is made available on a dedicated pin so that the user could implement additional functionality before
using this output (e.g., implement sticky nature of an unlock condition by routing it through an external set/reset
flip-flop).
By integrating the loop filter and making it programmable, the user can trade off both at runtime depending on the
quality of the incoming HS signal (inaccurate frequency, jitter content).
The filtered phase/frequency error value is now used to correct the programmed nominal DTO increment (NOM_INC
register value) to the instantaneous DTO increment (DTO_INC reported value). This updated DTO increment
determines the instantaneous DTO output frequency. By making DTO_INC available as a read-only register, the user
can read out via I²C and calculate the instantaneous frequency of the DTO generated clock.
Because of the digital nature of the PLL, the loop can be opened while still keeping an accurate frequency output.
Therefore, the PLL can also be used as a frequency synthesizer, without any HS reference. This is done by disabling
the PFD (PFD_DISABLE register value). This will keep DTO_INC always equal to NOM_INC, thereby producing a
DTO output frequency always equal to the desired programmed frequency, irrespective of HS.
There is a second option to operate in open loop though. In some video/graphics modes no valid HS is present during
a part of the frame/field period, typically during some lines of the VBI (vertical blanking interval). In order to have an
accurate PLL output clock and avoid clock drift, the PFD output needs to be held constant during this time. The PFD
FREEZE pin provides this option. Asserting this will freeze DTO_INC to its present value, thereby producing a
constant PLL output clock frequency, not necessarily equal to the nominal desired frequency programmed by
NOM_INC. Together with the composite sync slicer, this feature allows the use of the PLL for input signals with
embedded composite sync with minimal external logic. See Composite Sync Slicer section.
The phase of the PLL generated clock can be programmed in 31 uniform steps over a single clock period
(360/31 = 11.6 degrees phase resolution) so that the sampling phase of the ADC’s can be controlled accurately.
Next to sourcing the ADC channel clock from the PLL, the option exists to use an external pixel clock (from terminal
EXT_ADCCLK). If configured this way (via SEL_ADCCLK register value), a clock signal of the required sampling
frequency should be applied to EXT_ADCCLK and this signal, instead of the PLL generated clock, is routed to the
ADC channels. No phase control is available in this case on the external clock signal. Still, the internal PLL can be
used and its output available externally as explained below. This means two clock domains can be implemented on
THS8083: a first one from externally fed, a second one, possibly asynchronous to the first, generated by the internal
PLL. This provides considerable flexibility in the design of video/graphics equipment that implements scaling and
frame rate conversion.
2–6