THS8083 Datasheet, PDF (42/61 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL

4.2 Timing Diagram – 16-Bit Parallel Mode
This is the ITU.BT–601 style mode that will typically be used in YUV operation of the part with a Y analog input
connected to the Ch1 input of THS8083, Cb from Ch.2 input, and Cr from Ch.3 input. The DATACLK1 output is at
the sampling clock frequency and Ch3 remains unused. Output bus B of all channels is high impedance. The DHS
signal can be used to uniquely identify Cb from Cr output data.
ADCCLK2
DATACLK
CH1_OUTA[7..0]
CH1_OUTB[7..0]
CH2_OUTA[7..0]
CH2_OUTB[7..0]
CH3_OUTA[7..0]
CH3_OUTB[7..0]
HS
DHS
(DHS_POL = 0
Assumed-Inverted
Polarity Otherwise)
OE
pix 01
pix 02
Cb: From Ch.2 Input
Cr: From Ch.3 Input
7 ADCCLK2 Cycles Latency
tsu(OUT)
th(OUT)
Last Samples From Previous Line
01
02
03
tPLH(OE)
Last Samples From Previous Line 01(Cb)
tPHL(OE)
01(Cr)
03(Cb)
tsu(DHS)
th(DHS)
7 ADCCLK2
Cycles Latency
<DHS_MODE> = 1 –> Width
Equal to Width of HS Input
<DHS_MODE> = 0 –> DHS
Width is 1 ADCCLK2 Period
4–2