THS8083 Datasheet, PDF (4/61 Pages) Texas Instruments – Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL

3.2.12 Register Name: HS_WIDTH . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
3.2.13 Register Name: VS_WIDTH . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
3.2.14 Register Name: SYNC_CTRL . . . . . . . . . . . . . . . . . . . . . . . . 3–8
3.2.15 Register Name: LD_THRES . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
3.2.16 Register Name: PLL_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
3.2.17 Register Name: HS_COUNT_0 . . . . . . . . . . . . . . . . . . . . . . 3–9
3.2.18 Register Name: HS_COUNT_1 . . . . . . . . . . . . . . . . . . . . . . 3–10
3.2.19 Register Name: VS_COUNT_0 . . . . . . . . . . . . . . . . . . . . . . 3–10
3.2.20 Register Name: VS_COUNT_1 . . . . . . . . . . . . . . . . . . . . . . 3–10
3.2.21 Register Name: DTO_INC_0 . . . . . . . . . . . . . . . . . . . . . . . . 3–10
3.2.22 Register Name: DTO_INC_1 . . . . . . . . . . . . . . . . . . . . . . . . 3–10
3.2.23 Register Name: DTO_INC_2 . . . . . . . . . . . . . . . . . . . . . . . . 3–11
3.2.24 Register Name: DTO_INC_3 . . . . . . . . . . . . . . . . . . . . . . . . 3–11
3.2.25 Register Name: DTO_INC_4 . . . . . . . . . . . . . . . . . . . . . . . . 3–11
3.2.26 Register Name: SYNC_DETECT . . . . . . . . . . . . . . . . . . . . . 3–11
3.2.27 Register Name: CLP_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
3.2.28 Register Name: CLP_START_0 . . . . . . . . . . . . . . . . . . . . . . 3–12
3.2.29 Register Name: CLP_START_1 . . . . . . . . . . . . . . . . . . . . . . 3–12
3.2.30 Register Name: CLP_STOP_0 . . . . . . . . . . . . . . . . . . . . . . . 3–12
3.2.31 Register Name: CLP_STOP_1 . . . . . . . . . . . . . . . . . . . . . . . 3–12
3.2.32 Register Name: CH1_CLP . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
3.2.33 Register Name: CH1_COARSE . . . . . . . . . . . . . . . . . . . . . . 3–13
3.2.34 Register Name: CH1_FINE . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
3.2.35 Register Name: CH2_CLP . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
3.2.36 Register Name: CH2_COARSE . . . . . . . . . . . . . . . . . . . . . . 3–13
3.2.37 Register Name: CH2_FINE . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
3.2.38 Register Name: CH3_CLP . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
3.2.39 Register Name: CH3_COARSE . . . . . . . . . . . . . . . . . . . . . . 3–14
3.2.40 Register Name: CH3_FINE . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
3.2.41 Register Name: PIX_TRAP_0 . . . . . . . . . . . . . . . . . . . . . . . . 3–14
3.2.42 Register Name: PIX_TRAP_1 . . . . . . . . . . . . . . . . . . . . . . . . 3–14
3.2.43 Register Name: PWDN_CTRL . . . . . . . . . . . . . . . . . . . . . . . 3–14
3.2.44 Register Name: AUX_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
3.2.45 Register Name: CH1_RDBK . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
3.2.46 Register Name: CH2_RDBK . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
3.2.47 Register Name: CH3_RDBK . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
3.2.48 Register Name: OFM_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
4 Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4.1 Timing Diagram – 24-Bit Parallel Mode . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4.2 Timing Diagram – 16-Bit Parallel Mode . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
4.3 Timing Diagram – 48-Bit Interleaved Mode . . . . . . . . . . . . . . . . . . . . . . 4–3
4.4 Timing Diagram – 48-Bit Parallel Mode . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
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