LMH6521_16 Datasheet, PDF (4/29 Pages) Texas Instruments – High Performance Dual DVGA

LMH6521
SNOSB47D – MAY 2011 – REVISED MARCH 2013
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5V Electrical Characteristics ⁽¹⁾ (continued)
The following specifications apply for single supply with V+ = 5V, Differential V_OUT = 4V_PP, R_L= 200Ω, T_A=25°C, f_in = 200 MHz,
and Maximum Gain (0 attenuation). Boldface limits apply at temperature extremes.
Symbol
Parameter
Conditions
Min ⁽²⁾ Typ ⁽³⁾ Max ⁽²⁾
Units
Power Requirements
VCC
Supply Voltage
4.75
5.0
5.25
V
ICC
Supply Current
Both Channels Enabled
225
245
mA
ICC
Disabled Supply Current
Both Channels
35
mA
All Digital Inputs
Logic Compatibility
TTL, 2.5V CMOS, 3.3V CMOS
VIL
Logic Input Low Voltage
0.5
V
VIH
Logic Input High Voltage
1.8
V
IIH
Logic Input High Input Current
Digital Input Voltage = 5V
200
μA
IIL
Logic Input Low Input Current
Digital Input Voltage = 0V
–60
μA
Parallel and Pulse Mode Timing
t_GS
Setup Time
t_GH
Hold Time
t_LP
Latch Low Pulse Width
t_PG
Pulse Gap between Pulses
t_PW
Minimum Pulse Width
t_RW
Reset Width
Serial Mode Timing and AC Characteristics
Pulse Mode
3
ns
3
ns
7
ns
20
ns
15
ns
10
ns
SPI Compatible
f_SCLK
t_PH
t_PL
t_SU
t_H
t_OZD
Max Serial Clock Frequency
SCLK High State Duty Cycle
SCLK Low State Duty Cycle
Serial Data In Setup Time
Serial Data In Hold Time
Serial Data Out TRI-STATE-to-
Driven Time
% of SCLK Period
% of SCLK Period
Referenced to Negative edge of SCLK
50
MHz
50
%
50
%
2
ns
2
ns
10
ns
t_OD
Serial Data Out Output Delay Time Referenced to Negative edge of SCLK
t_CSS
Serial Chip Select Setup Time
Referenced to Positive edge of SCLK
10
ns
5
ns
CONNECTION DIAGRAM
A3/SDI/DNA 1
A4/CLK/UPA 2
A5 3
MOD0 4
MOD1 5
B5 6
B4/UPB 7
B3/DNB 8
LMH6521
GND
24 OUTA+
23 OUTA-
22 ENA
21 LATA
20 LATB
19 ENB
18 OUTB-
17 OUTB+
Figure 3. 32-Pin WQFN Package-Top View
4
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