LMH6521_16 Datasheet, PDF (19/29 Pages) Texas Instruments – High Performance Dual DVGA

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LMH6521
SNOSB47D – MAY 2011 – REVISED MARCH 2013
SCLK
t_PL
t_PH
t_SU
t_H
16^th clock
SDI
Valid Data
Valid Data
Figure 38. Write Timing, Data Written to SDI Pin
Parameter
t_PL
t_PH
t_SU
t_H
Table 4. Write Timing
Data Input on SDI Pin
Description
Minimum clock low time (clock duty dycle)
Minimum clock high time (clock duty cycle)
Input data setup time
Input data hold time
PULSE MODE (MOD1= 0, MOD0 = 1)
Pulse mode is a simple yet fast way to adjust gain settings. Using only two control lines per channel the
LMH6521 gain can be changed by simple up and down signals. Gain step sizes is selectable either by hard
wiring the board or using two additional logic inputs. For a system where gain changes can be stepped
sequentially from one gain to the next and where board space is limited this mode may be the best choice. The
ENA and ENB pins are fully active during pulse mode, and the channel gain state is preserved during the
disabled state. Refer to for pin definitions of the LMH6521 in pulse mode.
In this mode the gain step size can be selected from a choice of 0.5, 1, 2 or 6dB steps. During operation the gain
can be quickly adjusted either up or down one step at a time by a negative pulse on the UP or DN pins. As
shown in Figure 39 each gain step pulse must have a logic high state of at least t_PW= 20 ns and a logic low state
of at least t_PG= 20 ns for the pulse to register as a gain change signal.
PULSE TIMING
t_PW
t_PG
UP/DN
To provide a known gain state there is a reset feature in pulse mode. To reset the gain to maximum gain both
the UP and DN pins must be strobed low together as shown in Figure 39. There must be an overlap of at least
t_RW= 20 ns for the reset to register.
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