LMH6521_16 Datasheet, PDF (18/29 Pages) Texas Instruments – High Performance Dual DVGA

LMH6521
SNOSB47D – MAY 2011 – REVISED MARCH 2013
Control Logic
LMH6521
Clock out
Chip Select out
Data Out
Data In
CLK
CSb
SDI
SDO
R
20:
V+ (Logic High)
For SDO (MISO) pin only:
VOH = V+,
VOL = (V+) ± [0.012*(R+20) + Vcesat]
Recommended:
R = 300 Ohms to 2000 Ohms
V+ (Logic) = 2.5V to 3.3V
12 mA
Max
Figure 36. Serial Mode 4–wire Connection
SCLK
t_CSH
1^st clock
t_CSS
8^th clock
16^th clock
t_CSH
t_CSS
CSb
SDO
t_OZD
t_OD
D7 D1
t_ODZ
D0
Figure 37. Read Timing
Parameter
t_CSH
t_CSS
t_OZD
t_ODZ
t_OD
Table 3. Read Timing
Data Output on SDO Pin
Description
Chip select hold time
Chip select setup time
Initial output data delay
High impedance delay
Output data delay
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