LMH6521_16 Datasheet, PDF (17/29 Pages) Texas Instruments – High Performance Dual DVGA

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SCLK
LMH6521
SNOSB47D – MAY 2011 – REVISED MARCH 2013
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SCSb
COMMAND FIELD
DATA FIELD
C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
(MSB)
(LSB)
SDI
R/Wb 0 0 0 A3 A2 A1 A0
Write DATA
Reserved (3-bits)
Address (4-bits)
SDO
R/Wb
Reserved
ADDR:
DATA
C7
C6
0= write
0
1=read
Enable
0=Off
1=On
Gb5
1=+16dB
D7 D6 D5 D4 D3 D2 D1 D0
(MSB)
(LSB)
Hi-Z
Read DATA
Single Access Cycle
Data (8-bits)
Figure 35. Serial Interface Protocol (SPI compatible)
Read / Write bit. A value of 1 indicates a read operation, while a
value of 0 indicates a write operation.
Not used. Must be set to 0.
Address of register to be read or written.
In a write operation the value of this field will be written to the
addressed register when the chip select pin is deasserted. In a read
operation this field is ignored.
Table 1. Serial Word Format for LMH6521
C5
C4
C3
C2
C1
0
0
0
0
0
C0
0=Ch A
1=Ch B
Table 2. Serial Word Format for LMH6521 (cont)
Gb4
1=+8dB
Gb3
1=+4dB
Gb2
1=+2dB
Gb1
1=+1dB
Gb0
1=+0.5dB
RES
0
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