LMH6521_16 Datasheet, PDF (15/29 Pages) Texas Instruments – High Performance Dual DVGA

LMH6521
www.ti.com
SNOSB47D – MAY 2011 – REVISED MARCH 2013
PARALLEL MODE (MOD1= 1, MOD0 = 1)
When designing a system that requires very fast gain changes parallel mode is the best selection. Refer to for
pin definitions of the LMH6521 in parallel mode.
The LMH6521 has a 6-bit gain control bus as well as latch pins LATA and LATB for channels A and B. When the
latch pin is low, data from the gain control pins is immediately sent to the gain circuit (i.e. gain is changed
immediately). When the latch pin transitions high the current gain state is held and subsequent changes to the
gain set pins are ignored. To minimize gain change glitches multiple gain control pins should not change while
the latch pin is low. Gain glitches could result from timing skew between the gain set bits. This is especially the
case when a small gain change requires a change in state of three or more gain control pins. If continuous gain
control is desired the latch pin can be tied to ground. This state is called transparent mode and the gain pins are
always active. In this state the timing of the gain pin logic transitions should be planned carefully to avoid
undesirable transients
ENA and ENB pins are provided to reduce power consumption by disabling the highest power portions of the
LMH6521. The gain register will preserve the last active gain setting during the disabled state. These pins will
float high and can be left disconnected if they won't be used. If the pins are left disconnected a 0.01uF capacitor
to ground will help prevent external noise from coupling into these pins.
Figure 32, Figure 33, and Figure 34 show the various connections in parallel mode with respect to the latch pin.
CONTROL LOGIC
latcha
ga[5:0]
gb[5:0]
latchb
pd
DVGA
CONTROL LOGIC
latcha
cmode
V_SS
6
ga[5:0]
6
gb[5:0]
latchb
pd
ga[5:0]
gb[5:0]
pd
V_SS
6
6
V_SS
DVGA
latcha
cmode
V_SS
ga[5:0]
gb[5:0]
latchb
pd
Figure 32. Parallel Mode Connection for Fastest
Response
Figure 33. Parallel Mode Connection Not Using
Latch Pins (Latch pins tied to logic low state)
CONTROL LOGIC
latcha
6
ga/gb[5:0]
latchb
pd
DVGA
latcha
cmode
V_SS
ga[5:0]
gb[5:0]
latchb
pd
Figure 34. Parallel Mode Connection Using Latch Pins to Mulitplex Digital Data
SERIAL MODE — SPI COMPATIBLE INTERFACE (MOD1= 1, MOD0 = 0)
Serial interface allows a great deal of flexibility in gain programming and reduced board complexity. Using only 4
wires for both channels allows for significant board space savings. The trade off for this reduced board
complexity is slower response time in gain state changes. For systems where gain is changed only infrequently
or where only slow gain changes are required serial mode is the best choice. Refer to table for pin definitions of
the LMH6521 in serial mode.
The serial interface is a generic 4-wire synchronous interface that is compatible with SPI standard interfaces and
used on many microcontrollers and DSP controllers.
The serial mode is active when the two mode pins are set as follows: MOD1=1, MOD0=0). In this configuration
the pins function as shown in the table. The SPI interface uses the following signals: clock input (CLK), serial
data in (SDI), serial data out, and serial chip select (CS)
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