LMH6521_16 Datasheet, PDF (16/29 Pages) Texas Instruments – High Performance Dual DVGA

LMH6521
SNOSB47D – MAY 2011 – REVISED MARCH 2013
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ENA and ENB pins are active in serial mode. For fast disable capability these pins can be used and the serial
register will hold the last active gain state. These pins will float high and can be left disconnected for serial mode.
The serial control bus can also disable the DVGA channels, but at a much slower speed. The serial enable
function is an AND function. For a channel to be active both the enable pin and the serial control register must be
in the enabled state. To disable a channel either method will suffice. See Typical Performance Characteristics for
disable and enable timing information.
LATA and LATB pins are not active during serial mode.
The serial clock pin CLK is used to register the input data that is presented on the SDI pin on the rising edge;
and to source the output data on the SDO pin on the falling edge. User may disable clock and hold it in the low
state, as long as the clock pulse-width minimum specification is not violated when the clock is enabled or
disabled.
The chip select pin CS starts a new register access with each assertion - i.e., the SDATA field protocol is
required. The user is required to deassert this signal after the 16th clock. If the SCSb is deasserted before the
16th clock, no address or data write will occur. The rising edge captures the address just shifted-in and, in the
case of a write operation, writes the addressed register. There is a minimum pulse-width requirement for the
deasserted pulse - which is specified in Electrical Characteristics.
SDI is an input pin for the serial data. It must observe setup/hold requirements with respect to the SCLK. Each
cycle is 16-bits long
SDO is the data output pin and is normally at TRI-STATE and is driven only when SCSb is asserted. Upon SCSb
assertion, contents of the register addressed during the first byte are shifted out with the second 8 SCLK falling
edges. Upon power-up, the default register address is 00h
The SDO internal driver circuit is an open collector device with a weak pull-up resistor to an internal 2.5V
reference. It is 5V tolerant so an external pull-up resistor can connect to 2.5V, 3.3V or 5V as shown in Figure 36.
However, the external pull-up resistor should be chosen to limit the current to 11mA or less. Otherwise the SDO
logic low output level (V_OL may not achieve close to ground and in extreme case could cause problem for FPGA
input gate. Using minimum values for external pull-up resistor is a good to maximize speed for SDO signal. So if
high SPI clock frequency is needed then minimum value external pull-up resistor is the best choice as shown in
Figure 36.
Each serial interface access cycle is exactly 16 bits long as shown in Figure 35. Each signal's function is
described below. The read timing is shown in Figure 37, while the write timing is shown in figure Figure 38.
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