OMAP4430 Datasheet, PDF (385/443 Pages) Texas Instruments – Multimedia Device

Public Version
OMAP4430
www.ti.com
SWPS041D – DECEMBER 2010 – REVISED JANUARY 2012
(1) Related to the astm_clk maximum frequency.
(2) P = astm_clk period in ns
(3) The jitter probability density can be approximated by a Gaussian function.
(4) See DM Operating Condition Addendum for CORE OPP voltages.
astm_clk
astm_d[3:0]
STM1
STM2
STM3
STM4
STM4
STM4
STM4
Figure 6-130. STM—MIPI SDR Transmit Mode
SWPS040-092
6.8.2 JTAG Interface (JTAG)
The JTAG TAP controller handles standard IEEE JTAG interfaces. The following section defines the
Timing requirements for several tools used to test the OMAP4430 as:
• Free-running clock tool, like XDS560 and XDS510 tools
• Adaptive clock tool, like RealView® ICE tool and Lauterbach^TM tool
6.8.2.1 JTAG—Free-Running Clock Mode
Table 6-220 and Table 6-221 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 6-131).
Table 6-219. JTAG Timing Conditions—Free-running Clock Mode^(1)(3)(4)
TIMING CONDITION PARAMETER
VALUE
UNIT
MIN
MAX
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
PCB Conditions
5
ns
5
ns
Number of external peripherals
1
Far end load
Trace length
30
pF
See⁽²⁾
cm
Characteristics impedance
40
60
Ω
(1) Corresponding balls: AH2 / AG1 / AE3 / AH1 / AE1 / AE2
(2) Maximum PCB trace length = 5 cm and maximum cable = 15 cm
(3) For more information on JTAG ESD guideline example, see Section A.3.2.2.3, ESD Implementation—JTAG and cJTAG Interfaces.
(4) To have an idea of the output OMAP4 ball load supported for this application, you can consider the following:
Output OMAP4 ball load = Far End load + 1.34 pF/cm typical x trace length (cm).
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Timing Requirements and Switching Characteristics 385
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