OMAP4430 Datasheet, PDF (376/443 Pages) Texas Instruments – Multimedia Device

OMAP4430
Public Version
SWPS041D – DECEMBER 2010 – REVISED JANUARY 2012
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(1) In sdmmc2_dat[n:0], n up to 7
(2) See DM Operating Condition Addendum for CORE OPP voltages.
Table 6-207. MMC/SD/SDIO 2 Interface Switching Characteristics—Standard SDR JC64 Mode^(4)(5)(6)
NO.
PARAMETER
OPP100
OPP50
UNIT
MMC1
MMC2
MMC2
MMC5
1 / t_c(clk)
t_w(clkL)
t_w(clkH)
t_dc(clk)
t_j(clk)
t_R(clk)
t_F(clk)
t_d(clkH-cmdV)
Frequency⁽¹⁾ output sdmmc2_clk
Pulse duration, output sdmmc2_clk low
Pulse duration, output sdmmc2_clk high
Duty cycle error, output sdmmc2_clk
Jitter standard deviation⁽³⁾, output sdmmc2_clk
Rise time, output sdmmc2_clk
Fall time, output sdmmc2_clk
Delay time, sdmmc2_clk rising clock edge to
sdmmc2_cmd transition
MIN
MAX
24
0.5*P⁽²⁾
0.5*P⁽²⁾
–2083
2083
–400
400
7000
7000
4.1
37.2
MIN
MAX
24
0.5*P⁽²⁾
0.5*P⁽²⁾
–2083
2083
–400
400
7000
7000
4.1
37.2
MHz
ns
ns
ps
ps
ps
ps
ns
t_R(cmd)
Rise time, output sdmmc2_cmd
7000
7000
ps
t_F(cmd)
Fall time, output sdmmc2_cmd
7000
7000
ps
MMC6
t_d(clkH-doV)
Delay time, sdmmc2_clk rising clock edge to
4.1
37.2
4.1
37.2
ns
sdmmc2_dat[n:0] transition
t_R(DO)
t_F(do)
Rise time, output sdmmc2_dat[n:0]
Fall time, output sdmmc2_dat[n:0]
7000
7000
7000
ps
7000
ps
(1) Related to the output sdmmcx_clk maximum and minimum frequency.
(2) P = output sdmmcx_clk period in ns
(3) The jitter probability density can be approximated by a Gaussian function.
(4) In sdmmcx_dat[n:0], n up to 7
(5) In this section, the MMC/SD/SDIO output data and command signals are driven on the falling clock edge.
In this case, the MMCHS_HCTL[2] HSPE bit is set to 0. The controller is by default in this mode to maximize hold timings.
For more information, see MMC/SD/SDIO / MMC/SD/SDIO Functional Description / Output Signals Generation / Generation on Falling
Edge of MMC Clock section of the OMAP4430 TRM.
(6) See DM Operating Condition Addendum for CORE OPP voltages.
MMC1
MMC2
MMC2
sdmmc2_clk
MMC5
MMC5
sdmmc2_cmd
MMC6
MMC6
sdmmc2_dat[n:0]
SWPS040-085
Figure 6-123. MMC/SD/SDIO 2 Interface—Standard SDR JC64—Transmitter Mode⁽¹⁾⁽²⁾
(1) In sdmmc2_dat[n:0], n up to 7
(2) In this section, the MMC/SD/SDIO output data and command signals are driven on the falling clock edge.
In this case, the MMCHS_HCTL[2] HSPE bit is set to 0. The controller is by default in this mode to maximize hold timings.
For more information, see MMC/SD/SDIO / MMC/SD/SDIO Functional Description / Output Signals Generation / Generation on Falling
Edge of MMC Clock section of the OMAP4430 TRM.
376 Timing Requirements and Switching Characteristics
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