OMAP4430 Datasheet, PDF (135/443 Pages) Texas Instruments – Multimedia Device

Public Version
OMAP4430
www.ti.com
SWPS041D – DECEMBER 2010 – REVISED JANUARY 2012
(1) V_ITH is the voltage at which the receiver is required to detect a high state in the input signal.
(2) V_ITL is the voltage at which the receiver is required to detect a low state in the input signal. V_ITL is larger than the maximum single-ended
line high voltage during HS transmission. Therefore, both LP receivers will detect low during HS signaling.
(3) To reduce noise sensitivity on the received signal, the LP receiver is required to incorporate a hysteresis, V_HYST.
(4) V_ITL is the voltage at which the receiver is required to detect a low state in the input signal. Specification is relaxed for detecting 0 during
Ultralow-Power (ULP) state. The LP receiver is not required to detect HS single-ended voltage as 0 in this state.
(5) Excluding possible additional RF interference of 200 mV_PP beyond 450 MHz.
(6) This value includes a ground difference of 50 mV between the transmitter and the receiver, the static common-mode level tolerance and
variations below 450 MHz.
(7) This number is the transmitter V_ODMAX.
(8) Common mode is defined as the average voltage level of DX and DY: V_CM = (V_DX + V_DY)/2.
(9) Common mode ripple may be due to rise-fall time and transmission line impairments in the PCB.
(10) In vdda_y, y can have the value csi21 or csi22 depending on the ball used. For more information of the power supply name and the
corresponding pin, ball, see the POWER [9] column of Table 2-1.
(11) V_HYS is the magnitude of the difference between the positive-going threshold voltage V_T+ and the negative-going threshold voltage V_T–.
(12) The t_TIN (t_RIN and t_FIN also) value is the recommended condition. The t_TIN (t_RIN and t_FIN also) mismatch causes additional delay time
inside the device then leads to ac timing invalidation in this DM. The t_TIN (t_RIN and t_FIN also) mismatch does not necessarily mean
functional failure. This global value may be overridden on a per basis if another value is explicitly defined for that in the Timing
Requirements and Switching Characteristics Chapter of the data manual.
(13) The GPI mode is only available through multiplexing mode 3.
NOTE
For more information on the IO cell configurations (SC[1:0]), see the Control Module /
Control Module Functional Description / Functional Register Description / Signal Integrity
Parameter Control Registers With Pad Group Assignment section of the OMAP4430 TRM.
Table 3-8. Camera Control DC Electrical Characteristics
PARAMETER
Signals in Mode 0: cam_shutter, cam_strobe, cam_globalreset
(Bottom Balls : T27 / U27 / V27)
C_LOAD
Load capacitance
SC[1:0] = 00
SC[1:0] = 01
SC[1:0] = 10
t_OT
Output transition time (rise time, t_R or SC[1:0] = 00
fall time, t_F) measured between 10%
to 90% of PAD voltage, minimum at
SC[1:0] = 01
the minimum load and maximum at SC[1:0] = 10
the maximum load
1.2-V Mode
V_IH
Input high-level threshold
V_IL
V_HYS(1)
Input low-level threshold
Input hysteresis voltage
V_OH
Output high-level threshold (I_OH = –4 mA)
V_OL
Output low-level threshold (I_OL = 4 mA)
1.8-V Mode
V_IH
V_IL
V_HYS(1)
V_OH
V_OL
Input high-level threshold
Input low-level threshold
Input hysteresis voltage
Output high-level threshold (I_OH = –4 mA)
Output low-level threshold (I_OL = 4 mA)
MIN
4
2
7
1
0.4
0.6
0.65 * vdds_dv_cam
–0.3
135
0.75 * vdds_dv_cam
0.65 * vdds_dv_cam
–0.3
150
vdds_dv_cam – 0.45
NOM
MAX
60
21
33
15
5
7
vdds_dv_cam + 0.3
0.35 * vdds_dv_cam
0.25 * vdds_dv_cam
vdds_dv_cam + 0.3
0.35 * vdds_dv_cam
0.45
UNIT
pF
ns
V
V
mV
V
V
V
V
mV
V
V
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Electrical Characteristics 135