OMAP4430 Datasheet, PDF (353/443 Pages) Texas Instruments – Multimedia Device

Public Version
OMAP4430
www.ti.com
SWPS041D – DECEMBER 2010 – REVISED JANUARY 2012
Table 6-182. UART IO Settings References
MULTIPLEXING
MODES
UART1
Mode1
Mode2
UART2
IO SET 1
IO SET 2
IO SETTINGS REFERENCES
IO SET 3
IO SET 4
IO SET 5
Balls: C26 / D26
Signals: uart2_rx,
uart1_tx
For more
information
regarding LB[1:0]
Far End Load IO
settings, see
Control Module /
Control Module
Functional
Description/
Functional
Register
Description / I2Cx
I/Os Group
Pullupresx
Controls and Load
Range Settings
section of
OMAP4430 TRM.
Balls: AF23 / F27
Signals: uart1_rx,
uart1_tx
For more
information
regarding LB[1:0]
and SC[1:0] Far
End Load IO
settings, see
Control Module /
Control Module
Functional
Description/
Functional
Register
Description /
Low-Speed I/Os
Combined Slew
Rate Versus TL
Length and Load
Settings section of
OMAP4430 TRM.
Balls: AG23 /
AH23
Signals: uart1_cts,
uart1_rts
For more
information
regarding MB[1:0]
and LB0 Far End
Load IO settings,
see Control
Module / Control
Module Functional
Description/
Functional
Register
Description / 50-Ω
Output Buffer I/Os
With Combined
Mode and Load
Settings section of
OMAP4430 TRM.
Ball: E3
Ball: AA3
Signal: uart1_rx Signal: uart1_rx
For more
For more
information on
information
SDMMC1_DR[2:0] regarding DS0 Far
_SPEEDCTRL
End Load IO
registers see:
settings, see
Control Module / Control Module /
Control Module Control Module
Functional
Functional
Description /
Description/
Functional
Functional
Register
Register
Description /
Description / I/O
Signal Integrity
Cells With
Parameter Control Configurable
Registers With
Output Driver
Pad Group
Impedance section
Assignment /
of OMAP4430
Device Interfaces TRM.
Signal Group
Controls Mapping
section
or,
Control Module /
Control Module
Register Manual /
SYSCTRL_PADC
ONF_CORE
Register
Description section
of the OMAP4430
TRM.
IO SET 6
Copyright © 2010–2012, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 353
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