OMAP4430 Datasheet, PDF (281/443 Pages) Texas Instruments – Multimedia Device

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OMAP4430
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SWPS041D – DECEMBER 2010 – REVISED JANUARY 2012
Table 6-63. McBSP4 Switching Characteristics—I2S/PCM—Slave Mode⁽¹⁾⁽²⁾
NO.
PARAMETER
OPP100
OPP50
UNIT
MIN
MAX
MIN
MAX
BS5
t_{d(clkxAE-dxV)}
Delay time, input mcbsp4_clkx active edge to
0.9
23.2
1.0
40.0
ns
output mcbsp4_dx valid
t_R(dx)
t_F(dx)
Rise time, output mcbsp4_dx
Fall time, output mcbsp4_dx
400
6500
400
6500
ps
400
6500
400
6500
ps
(1) The timings apply to all configurations regardless of mcbsp4_clk polarity and which clock edges are used to drive output data and
capture input data.
(2) See DM Operating Condition Addendum for CORE OPP voltages.
6.6.1.3.2 McBSP4—I2S/PCM—Half-Cycle—24-MHz Master and 12-MHz Slave
Table 6-65 through Table 6-68 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
Table 6-64. McBSP4 Timing Conditions—I2S/PCM^(1)(2)(3)
SYSTEM CONDITION PARAMETER
VALUE
UNIT
MIN
MAX
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
PCB Conditions
400
6500
ps
400
6500
ps
Number of external peripherals
1
Far end load
5
pF
Trace length, point-to-point interconnect
9
cm
Characteristics impedance
30
55
Ω
(1) IO settings: MB[1:0] = 10 and LB0 = 0.
For more information, see Control Module / Control Module Functional Description/ Functional Register Description / Signal Integrity
Parameter Control Registers with Pad Group Assignment / I/Os with Combined Mode and Load Settings section of the OMAP4430
TRM.
(2) In this table the rise and fall times are calculated for 10% to 90% of VDDS. For more information on the corresponding OMAP4 VDDS
power supply name, see Table 2-1, POWER [9] column with the ball name.
(3) To have an idea of the output OMAP4 ball load supported for this application, you can consider the following:
Output OMAP4 ball load = Far End load + 1.34 pF/cm typical x trace length (cm).
6.6.1.3.2.1 McBSP4—I2S/PCM—Half-Cycle—24-MHz Master Mode
Table 6-65. McBSP4 Timing Requirements—I2S/PCM—Master Mode⁽¹⁾⁽³⁾
NO.
PARAMETER
OPP100
OPP50
UNIT
MIN
MAX
MIN
MAX
BM5
t_{su(drV-clkAE)}
Setup time, mcbsp4_dr valid before
5.3
11.6
ns
mcbsp4_clk⁽²⁾ active edge
BM6
t_h(clkAE-drV)
Hold time, mcbsp4_dr valid after
5.3
11.3
ns
mcbsp4_clk⁽²⁾ active edge
(1) The timings apply to all configurations regardless of mcbsp4_clk polarity and which clock edges are used to drive output data and
capture input data.
(2) mcbsp4_clk corresponds to either mcbsp4_clkx or mcbsp4_clkr; mcbsp4_clkr is available in 6-pin mode only.
(3) See DM Operating Condition Addendum for CORE OPP voltages.
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Timing Requirements and Switching Characteristics 281
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