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TMS320DM8168_13 Datasheet, PDF (37/327 Pages) Texas Instruments – TMS320DM816x DaVinci Video Processors
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TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
2.10.5 C674x Memory Map
Because the C674x DSP has specific hardwired address decoding built in, the C674x memory map is
slightly different than that of the Cortex™-A8. The C674x has a separate CFG bus which is used to
access L4 peripherals and its UMAP1 bus has a direct connection into HDVICP2 SL2 (HDVICP2-0 and
HDVICP2-1 only) memories. All C674x MDMA port accesses are routed through the System MMU for
address translation.
Table 2-31. C674x Memory Map
REGION NAME
Reserved (1)
UMAP1 (1)
Reserved (UMAP1)(1)
UMAP1 (1)
Reserved (UMAP1)(1)
Reserved (1)
L2 SRAM(1)
Reserved (1)
L1P SRAM(1)
Reserved (1)
L1D SRAM(1)
Reserved (1)
Internal CFG(2)(3)
Reserved (3)
L4 Standard Domain(3)
EDMA TPCC(3)
Reserved (3)
EDMA TPTC0(3)
EDMA TPTC1(3)
EDMA TPTC2(3)
EDMA TPTC3(3)
Reserved (3)
START ADDRESS
(HEX)
0x0000 0000
0x0040 0000
0x0044 0000
0x0050 0000
0x0054 0000
0x0060 0000
0x0080 0000
0x0084 0000
0x00E0 0000
0x00E0 8000
0x00F0 0000
0x00F0 8000
0x0180 0000
0x01C0 0000
0x0800 0000
0x0900 0000
0x0910 0000
0x0980 0000
0x0990 0000
0x09A0 0000
0x09B0 0000
0x09C0 0000
END ADDRESS (HEX)
0x003F FFFF
0x0043 FFFF
0x004F FFFF
0x0053 FFFF
0x005F FFFF
0x007F FFFF
0x0083 FFFF
0x00DF FFFF
0x00E0 7FFF
0x00EF FFFF
0x00F0 7FFF
0x017F FFFF
0x01BF FFFF
0x07FF FFFF
0x08FF FFFF
0x090F FFFF
0x097F FFFF
0x098F FFFF
0x099F FFFF
0x09AF FFFF
0x09BF FFFF
0x09FF FFFF
SIZE
4MB
256KB
768KB
256KB
768KB
2MB
256KB
5888KB
32KB
992KB
32KB
9184KB
4MB
100MB
16MB
1MB
7MB
1MB
1MB
1MB
1MB
4MB
DESCRIPTION
Reserved
C674x UMAP1 (HDVICP2-0 SL2)
Reserved
C674x UMAP1 (HDVICP2-1 SL2)
Reserved
Reserved
C674x UMAP0 (L2 RAM)
Reserved
C674x L1P Cache and RAM
Reserved
C674x L1D Cache and RAM
Reserved
C674x Internal CFG registers
Reserved
Peripheral Domain (see Table 2-27)
EDMA TPCC Registers
Reserved
EDMA TPTC0 Registers
EDMA TPTC1 Registers
EDMA TPTC2 Registers
EDMA TPTC3 Registers
Reserved
L4 High-Speed
Domain (3)
Reserved (3)
C674x L1 and L2(4)
MDMA L3(5)
0x0A00 0000
0x0B00 0000
0x1000 0000
0x1100 0000
0x0AFF FFFF
0x0FFF FFFF
0x10FF FFFF
0xFFFF FFFF
16MB Peripheral Domain (see Table 2-28)
80MB
16MB
3824MB
Reserved
C674x Internal Global Address
System MMU Mapped L3 Regions
(1) Addresses 0x0000 0000 to 0x017F FFFF are internal to the C674x device.
(2) Addresses 0x0180 0000 to 0x01BF FFFF are reserved for C674x internal CFG registers.
(3) Addresses 0x01C0 0000 to 0x0FFF FFFF are mapped to the C674x CFG bus.
(4) Addresses 0x1000 0000 to 0x10FF FFFF are mapped to C674x internal addresses 0x0000 0000 to 0x00FF FFFF.
(5) These accesses are routed through the System MMU where the page tables translate to the physical L3 addresses shown in Table 2-
26.
Copyright © 2011–2013, Texas Instruments Incorporated
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