TMS320DM8168_13 Datasheet, PDF (300/327 Pages) Texas Instruments – TMS320DM816x DaVinci Video Processors

TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
8.18.2 SPI Electrical Data and Timing
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Table 8-101. Timing Requirements for SPI - Master Mode
(see Figure 8-84 and Figure 8-85)
NO.
MIN
MAX UNIT
1 t_c(SPICLK)
2 t_w(SPICLKL)
3 t_w(SPICLKH)
4 t_{su(MISO-SPICLK)}
5 t_{h(SPICLK-MISO)}
6 t_{d(SPICLK-MOSI)}
7 t_d(SCS-MOSI)
8 t_{d(SCS-SPICLK)}
9 t_{d(SPICLK-SCS)}
MASTER: 1 LOAD AT A MAXIMUM OF 5 pF
Cycle time, SPI_CLK⁽¹⁾⁽²⁾
Pulse duration, SPI_CLK low⁽¹⁾
Pulse duration, SPI_CLK high⁽¹⁾
Setup time, SPI_D[x] valid before SPI_CLK active edge⁽¹⁾
Hold time, SPI_D[x] valid after SPI_CLK active edge⁽¹⁾
Delay time, SPI_CLK active edge to SPI_D[x] transition⁽¹⁾
Delay time, SPI_SCS[x] active edge to SPI_D[x] transition
Delay time, SPI_SCS[x] active to SPI_CLK
first edge⁽¹⁾
MASTER_PHA0 ⁽⁵⁾
MASTER_PHA1 ⁽⁵⁾
Delay time, SPI_CLK last edge to SPI_SCS[x] ^{MASTER_PHA0(5)}
inactive ⁽¹⁾
MASTER_PHA1 ⁽⁵⁾
20.8 ⁽³⁾
0.5*P - 1⁽⁴⁾
0.5*P - 1⁽⁴⁾
2.29
2.67
-3.57
B-4.2 ⁽⁶⁾
A-4.2 ⁽⁷⁾
A-4.2 ⁽⁷⁾
B-4.2 ⁽⁶⁾
ns
ns
ns
ns
ns
3.57 ns
3.57 ns
ns
ns
ns
ns
1 t_c(SPICLK)
2 t_w(SPICLKL)
3 t_w(SPICLKH)
4 t_{su(MISO-SPICLK)}
5 t_{h(SPICLK-MISO)}
6 t_{d(SPICLK-MOSI)}
7 t_d(SCS-MOSI)
8 t_{d(SCS-SPICLK)}
9 t_{d(SPICLK-SCS)}
MASTER: UP TO 4 LOADS AT A MAXIMUM TOTAL OF 25 pF
Cycle time, SPI_CLK⁽¹⁾⁽²⁾
Pulse duration, SPI_CLK low⁽¹⁾
Pulse duration, SPI_CLK high⁽¹⁾
Setup time, SPI_D[x] valid before SPI_CLK active edge⁽¹⁾
Hold time, SPI_D[x] valid after SPI_CLK active edge⁽¹⁾
Delay time, SPI_CLK active edge to SPI_D[x] transition⁽¹⁾
Delay time, SPI_SCS[x] active edge to SPI_D[x] transition
Delay time, SPI_SCS[x] active to SPI_CLK
first edge⁽¹⁾
MASTER_PHA0 ⁽⁵⁾
MASTER_PHA1 ⁽⁵⁾
Delay time, SPI_CLK last edge to SPI_SCS[x] ^{MASTER_PHA0(5)}
inactive ⁽¹⁾
MASTER_PHA1 ⁽⁵⁾
41.7 ⁽⁸⁾
0.5*P - 2⁽⁴⁾
0.5*P - 2⁽⁴⁾
3.02
2.76
-4.62
B-2.54 ⁽⁶⁾
A-2.54 ⁽⁷⁾
A-2.54 ⁽⁷⁾
B-2.54 ⁽⁶⁾
ns
ns
ns
ns
ns
4.62 ns
4.62 ns
ns
ns
ns
ns
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) Related to the SPI_CLK maximum frequency.
(3) Maximum frequency = 48 MHz
(4) P = SPICLK period.
(5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
(6) B = (TCS + 0.5) * TSPICLKREF * F_ratio, where TCS is a bit field of the SPI_CH(i)CONF register and F_ratio = Even ≥2.
(7) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS
+ 0.5) * F_ratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
(8) Maximum frequency = 24 MHz
300 Peripheral Information and Timings
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