TMS320DM8168_13 Datasheet, PDF (263/327 Pages) Texas Instruments – TMS320DM816x DaVinci Video Processors

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TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
• Availability of a combination of these digital video input and output port configurations, control signals
for multiple 8-bit ports, as well as separate synchronization signals is limited by the device pin
multiplexing (for details, see Section 4.5). The following video inputs and outputs are not multiplexed
and are always available:
– SD DAC composite, S-video, component out
– HD DAC component out
– HDMI output (same as VOUT[1])
– 16-bit VOUT[0] (embedded sync)
– Single 16-bit, dual 8-bit VIN[0] (embedded sync).
• Graphics features:
– Three independently-generated graphics layers.
– Each supports full-screen resolution graphics in HD, SD or both.
– Up and down scaler optimized for graphics.
– Global and pixel-level alpha blending supported.
• Discrete external HSYNC and VSYNC signals for the HD-DAC are available on silicon revision 2.x
devices. These signals are mapped to the following pins (for details, see Section 3.2.20):
– HSYNC - AR5, AT9, AR8
– VSYNC - AL5, AP9, AL9
The functionality of these pins is set using the SPARE_CTRL0 register (address: 0x4814 0724).
Figure 8-67 and Table 8-70 describe the SPARE_CTRL0 register.
Note: When changing this register, read original value and write back same value in Reserved
fields.
For example, these are the steps required to use the pins AR8 and AL9 as the DAC_HSYNC and
VSYNC signals:
1. Set the PINCTRLx registers for AR8 and AL9 as follows:
• 0x4814 0894 = 0x00000001
• 0x4814 0898 = 0x00000001
2. Select analog VENC sync out option as follows:
• 0x4814 0724 = 0x00000004
31
Reserved
3
2
1
0
SPR_CTL0_2 SPR_CTL0_1 Rsvd
Figure 8-67. SPARE_CTRL0 Register
Bit Field
31:3 Reserved
2 SPR_CTL0_2
1 SPR_CTL0_1
0 Reserved
Table 8-70. SPARE_CTRL0 Register Field Descriptions
Value
0
0
1
0
1
0
Description
Reserved
To Select DAC or VOUT[0] Source Signals
Selects VOUT[0]_AVID and VOUT[0]_FLD
Selects DAC_HSYNC and DAC_VSYNC
To Select DAC or VOUT[1] Source Signals
Selects VOUT[1]_HSYNC and VOUT[1]_VSYNC
Selects DAC_HSYNC and DAC_VSYNC
Reserved
For more detailed information on specific features, see the HDVPSS chapter in the TMS320DM816x
DaVinci Digital Media Processors Technical Reference Manual (literature number SPRUGX8).
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Peripheral Information and Timings 263
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