TMS320DM8168_13 Datasheet, PDF (145/327 Pages) Texas Instruments – TMS320DM816x DaVinci Video Processors

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TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
system) while keeping the POR pin asserted (low).
3. Once the power supplies and the input clock source are stable, the POR pin must remain asserted
(low) for a minimum of 32 DEV_MXI cycles. Within the low period of the POR pin, the following
happens:
(a) All pins enter a Hi-Z mode.
(b) The PRCM asserts reset to all modules within the device.
(c) The PRCM begins propagating these clocks to the chip with the PLLs in bypass mode.
4. The POR pin may now be deasserted (driven high). When the POR pin is deasserted (high):
(a) The BOOT pins are latched.
(b) Reset to the ARM Cortex-A8 is de-asserted, provided the processor clock is running.
(c) All other domain resets are released, provided the domain clocks are running.
(d) The clock, reset, and power-down state of each peripheral is determined by the default settings of
the PRCM.
(e) The ARM Cortex-A8 begins executing from the default address (Boot ROM).
7.2.3 External Warm Reset (RESET pin)
An external warm reset is activated by driving the RESET pin active-low. This resets everything in the
device, except the ARM Cortex-A8 interrupt controller, test, and emulation. An emulator session stays
alive during warm reset.
The following sequence must be followed during a warm reset:
1. Power supplies and input clock sources should already be stable.
2. The RESET pin must be asserted (low) for a minimum of 32 DEV_MXI cycles. Within the low period of
the RESET pin, the following happens:
(a) All pins, except test and emulation pins, enter a Hi-Z mode.
(b) The PRCM asserts reset to all modules within the device, except for the ARM Cortex-A8 interrupt
controller, test, and emulation.
(c) RSTOUT is asserted.
3. The RESET pin may now be de-asserted (driven high). When the RESET pin is de-asserted (high):
(a) The BOOT pins are latched.
(b) Reset to the ARM Cortex-A8 and modules without a local processor is de-asserted, with the
exception of the ARM Cortex-A8 interrupt controller, test, and emulation.
(c) RSTOUT is de-asserted.
(d) The clock, reset, and power-down state of each peripheral is determined by the default settings of
the PRCM.
(e) The ARM Cortex-A8 begins executing from the default address (Boot ROM).
(f) Since the ARM Cortex-A8 interrupt controller is not impacted by warm reset, application software
needs to explicitly clear all pending interrupts in the ARM Cortex-A8 interrupt controller.
7.2.4 Emulation Warm Reset
An emulation warm reset is activated by the on-chip emulation module. It has the same effect and
requirements as an external warm reset (RESET), with the exception that it does not re-latch the BOOT
pins.
The emulator initiates an emulation warm reset via the ICEPick module. To invoke the emulation warm
reset via the ICEPick module, the user can perform the following from the Code Composer Studio™ IDE
menu:
Debug → Advanced Resets → System Reset.
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Power, Reset, Clocking, and Interrupts 145
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