TMS320DM8168_13 Datasheet, PDF (292/327 Pages) Texas Instruments – TMS320DM816x DaVinci Video Processors

TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
HEX ADDRESS
0x4806 0250
0x4806 0254
0x4806 0258
0x4806 025C
0x4806 02FC
Table 8-90. SD and SDIO Registers⁽¹⁾ (continued)
ACRONYM
SD_FE
SD_ADMAES
SD_ADMASAL
SD_ADMASAH
SD_REV
REGISTER NAME
Force Event
ADMA Error Status
ADMA System address Low bits
ADMA System address High bits
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8.16.2 SD and SDIO Electrical Data and Timing
8.16.2.1 SD Identification and Standard SD Mode
Table 8-91. Timing Requirements for SD and SDIO—SD Identification and Standard SD Mode
(see Figure 8-80, Figure 8-82)
NO.
MIN
MAX UNIT
SD Identification Mode
1 t_{su(CMDV-CLKH)}
Setup time, SD_CMD valid before SD_CLK rising clock edge
1198.2
ns
2 t_{h(CLKH-CMDIV)}
Hold time, SD_CMD valid after SD_CLK rising clock edge
1249.0
ns
Standard SD Mode
1 t_{su(CMDV-CLKH)}
Setup time, SD_CMD valid before SD_CLK rising clock edge
6.0
ns
2 t_{h(CLKH-CMDIV)}
Hold time, SD_CMD valid after SD_CLK rising clock edge
19.2
ns
3 t_{su(DATV-CLKH)}
Setup time, SD_DATx valid before SD_CLK rising clock edge
6.0
ns
4 t_h(CLKH-DATV)
Hold time, SD_DATx valid after SD_CLK rising clock edge
19.2
ns
Table 8-92. Switching Characteristics Over Recommended Operating Conditions for SD and SDIO—SD
Identification and Standard SD Mode
(see Figure 8-79, Figure 8-80, Figure 8-81, Figure 8-82)
NO.
PARAMETER
MIN
MAX UNIT
SD Identification Mode
8
f_op(CLKID)
t_c(CLKID)
13 t_d(CLKH-CMD)
Standard SD Mode
Identification mode frequency, SD_CLK
Identification mode period, SD_CLK
Delay time, SD_CLK rising clock edge to SD_CMD transition
2500.0
6.5
400 kHz
ns
2492.5 ns
7
f_op(CLK)
t_c(CLK)
9 t_w(CLKL)
10 t_w(CLKH)
13 t_d(CLKH-CMD)
14 t_d(CLKH-DAT)
Operating frequency, SD_CLK
Operating period, SD_CLK
Pulse duration, SD_CLK low
Pulse duration, SD_CLK high
Delay time, SD_CLK rising clock edge to SD_CMD transition
Delay time, SD_CLK rising clock edge to SD_DATx transition
41.7
0.45*P ⁽¹⁾
0.45*P ⁽¹⁾
6.3
6.3
24
0.55*P ⁽¹⁾
0.55*P ⁽¹⁾
35.3
35.3
MHz
ns
ns
ns
ns
ns
(1) P = SD_CLK period.
8.16.2.2 High-Speed SD Mode
Table 8-93. Timing Requirements for SD and SDIO—High-Speed SD Mode
(see Figure 8-80, Figure 8-82)
NO.
MIN
1 t_{su(CMDV-CLKH)}
Setup time, SD_CMD valid before SD_CLK rising clock edge
4.1
2 t_h(CLKH-CMDV)
Hold time, SD_CMD valid after SD_CLK rising clock edge
1.9
3 t_{su(DATV-CLKH)}
Setup time, SD_DATx valid before SD_CLK rising clock edge
4.1
4 t_h(CLKH-DATV)
Hold time, SD_DATx valid after SD_CLK rising clock edge
1.9
MAX
UNIT
ns
ns
ns
ns
292 Peripheral Information and Timings
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