TMS320DM8168_13 Datasheet, PDF (1/327 Pages) Texas Instruments – TMS320DM816x DaVinci Video Processors

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TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614D – MARCH 2011 – REVISED JANUARY 2013
TMS320DM816x DaVinci Video Processors
Check for Samples: TMS320DM8168, TMS320DM8167, TMS320DM8166, TMS320DM8165
1 Device Summary
1.1 Features
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• High-Performance DaVinci™ Video Processors
– 2 SP x SP → DP Every Two Clocks
– ARM^® Cortex™-A8 RISC Processor
– 2 SP x DP → DP Every Three Clocks
• Up to 1.35 GHz
– 2 DP x DP → DP Every Four Clocks
– C674x VLIW DSP
• Up to 1.125 GHz
• Up to 9000 MIPS and 6750 MFLOPS
• Fully Software-Compatible with C67x+™
and C64x+™
• ARM^® Cortex™-A8 Core
– ARMv7 Architecture
• In-Order, Dual-Issue, Superscalar
Processor Core
• NEON™ Multimedia Architecture
– Supports Integer and Floating Point (VFPv3-
IEEE754 compliant)
• Jazelle^® RCT Execution Environment
• ARM^® Cortex™-A8 Memory Architecture
– 32K-Byte Instruction and Data Caches
– 256K-Byte L2 Cache
– 64K-Byte RAM, 48K-Byte Boot ROM
• Fixed-Point Multiply Supports Two 32 x
32 Multiplies, Four 16 x 16-bit Multiplies
including Complex Multiplies, or Eight 8 x
8-Bit Multiplies per Clock Cycle
• C674x Two-Level Memory Architecture
– 32K-Byte L1P and L1D RAM and Cache
– 256K-Byte L2 Unified Mapped RAM and
Caches
• System Memory Management Unit (System
MMU)
– Maps C674x DSP and EMDA TCB Memory
Accesses to System Addresses
• 512K-Bytes On-Chip Memory Controller
(OCMC) RAM
• Media Controller
– Manages HDVPSS and HDVICP2 modules
• Up to Three Programmable High-Definition
Video Image Coprocessing (HDVICP2) Engines
• TMS320C674x Floating-Point VLIW DSP
– Encode, Decode, Transcode Operations
– 64 General-Purpose Registers (32-Bit)
– H.264, MPEG2, VC1, MPEG4 SP and ASP
– Six ALU (32-Bit and 40-Bit) Functional Units
• SGX530 3D Graphics Engine (available only on
• Supports 32-Bit Integer, SP (IEEE Single
the DM8168 and DM8166 device)
Precision, 32-Bit) and DP (IEEE Double
Precision, 64-Bit) Floating Point
• Supports up to Four SP Adds Per Clock
and Four DP Adds Every Two Clocks
• Supports up to Two Floating-Point (SP or
DP) Approximate Reciprocal or Square
Root Operations Per Cycle
– Two Multiply Functional Units
• Mixed-Precision IEEE Floating-Point
Multiply Supported up to:
– 2 SP x SP → SP Per Clock
– Delivers up to 30 MTriangles per second
– Universal Scalable Shader Engine
– Direct3D^® Mobile, OpenGL^® ES 1.1 and 2.0,
OpenVG™ 1.1, OpenMax™ API Support
– Advanced Geometry DMA Driven Operation
– Programmable HQ Image Anti-Aliasing
• Endianness
– ARM, DSP Instructions and Data – Little
Endian
• HD Video Processing Subsystem (HDVPSS)
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DaVinci, C64x+, SmartReflex, TMS320C6000, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas
2
Instruments.
Cortex, NEON are trademarks of ARM Ltd or its subsidiaries.
3
ARM, Jazelle, Thumb are registered trademarks of ARM Ltd or its subsidiaries.
4
USSE, POWERVR are trademarks of Imagination Technologies Limited.
5
OpenVG, OpenMax are trademarks of Khronos Group Inc.
6
Direct3D, Microsoft, Windows are registered trademarks of Microsoft Corporation in the United States and/or other countries.
7
I²C BUS is a registered trademark of NXP B.V. Corporation Netherlands.
8
PCI Express, PCIe are registered trademarks of PCI-SIG.
9
OpenGL is a registered trademark of Silicon Graphics International Corp. or its subsidiaries in the United States and/or other
10
countries.
All other trademarks are the property of their respective owners.
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PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated