BQ24618_15 Datasheet, PDF (33/43 Pages) Texas Instruments – System Power Selector and Low

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bq24618
SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015
10 Power Supply Recommendations
For proper operation of bq2461x, VCC must be from 5 V to 28 V (bq24610) or 24 V (bq24617). To begin
charging, VCC must be higher than SRN by at least 500 mV (otherwise, the device will be in sleep mode). TI
recommends an input voltage of at least 1.5 V to 2 V higher than the battery voltage, taking into consideration
the DC losses in the high-side FET (Rdson), inductor (DCR), and input sense resistor (between ACP and ACN),
the body diode drop of RBFET between VCC and input power supply, and battery sense resistor (between SRP
and SRN). Power limit for the input supply must be greater than the max power required by either the system
load or for battery charging (the greater of the two).
11 Layout
11.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize the high-frequency current-path loop (see Figure 23) is important to prevent electrical
and magnetic field radiation and high-frequency resonance problems. The following is a PCB layout priority list
for proper layout. Layout of the PCB according to this specific order is essential.
1. Place the input capacitor as close as possible to the switching MOSFET supply and ground connections, and
use the shortest-possible copper trace connection. These parts should be placed on the same layer of PCB,
instead of on different layers using vias to make the connection.
2. The IC should be placed close to the switching MOSFET gate terminals to keep the gate-drive signal traces
short for a clean MOSFET drive. The IC can be placed on the other side of the PCB from the switching
MOSFETs.
3. Place the inductor input terminal as close as possible to the switching MOSFET output terminal. Minimize the
copper area of this trace to lower electrical and magnetic field radiation, but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging-current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in the same layer, close to each other (minimize
loop area), and do not route the sense leads through a high-current path (see Figure 24 for the Kelvin
connection for best current accuracy). Place decoupling capacitors on these traces next to the IC.
5. Place the output capacitor next to the sensing resistor output and ground.
6. The output capacitor ground connections must be tied to the same copper that connects to the input
capacitor ground before connecting to system ground.
7. Route the analog ground separately from the power ground and use a single ground connection to tie the
charger power ground to the charger analog ground. Just beneath the IC, use the copper pour for analog
ground, but avoid the power pins to reduce inductive and capacitive noise coupling. Connect the analog
ground to GND. Connect the analog ground and power ground together using the thermal pad as the single
ground connection point. Alternatively, use a 0-Ω resistor to tie the analog ground to power ground (the
thermal pad should tie to analog ground in this case). A star-connection under the thermal pad is highly
recommended.
8. It is critical to solder the exposed thermal pad on the back side of the IC package to the PCB ground. Ensure
that there are sufficient thermal vias directly under the IC connecting to the ground plane on the other layers.
9. Place decoupling capacitors next to the IC pins, and make the trace connection as short as possible.
10. All via sizes and numbers must be adequate for a given current path.
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