BQ24618_15 Datasheet, PDF (19/43 Pages) Texas Instruments – System Power Selector and Low

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bq24618
SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015
Feature Description (continued)
• TS voltage goes out of range, indicating the battery temperature is too hot or too cold.
• TTC safety timer times out.
8.3.8 System Power Selector
The bq24618 automatically switches adapter or battery power to the system load. The battery is connected to the
system by default during power up or during SLEEP mode. The battery is disconnected from the system, and
then the adapter is connected to the system 30 ms after exiting SLEEP. An automatic break-before-make logic
prevents shoot-through currents when the selectors switch.
The ACDRV is used to drive a pair of back-to-back P-channel power MOSFETs between the adapter and ACP
with sources connected together and to VCC. The FET connected to the adapter prevents reverse discharge
from the battery to the adapter when turned off. The P-channel FET with the drain connected to the adapter input
provides reverse battery discharge protection when off; and also minimizes system power dissipation with its low
r_DS(on), compared to a Schottky diode. The other P-channel FET connected to ACP separates the battery from
the adapter and provides a limited dI/dt when connecting the adapter to the system by controlling the FET turnon
time. The BATDRV controls a P-channel power MOSFET placed between BAT and the system.
When an adapter is not detected, the ACDRV is pulled to VCC to keep ACFET off, disconnecting the adapter
from system. BATDRV stays at ACN-6V to connect the battery to the system.
Approximately 30 ms after the device comes out of SLEEP mode, the system begins to switch from battery to
adapter. The break-before-make logic keeps both ACFET and BATFET off for 10 µs before ACFET turns on.
This prevents shoot-through current or any large discharging current from going into the battery. BATDRV is
pulled up to ACN and the ACDRV pin is set to VCC-6V by an internal regulator to turn on P-channel ACFET,
connecting the adapter to the system.
When the adapter is removed, the system waits until VCC drops back to within 200 mV above SRN to switch
from the adapter back to the battery. The break-before-make logic still keeps 10-μs dead time. The ACDRV is
pulled up to VCC and the BATDRV pin is set to ACN-6V by an internal regulator to turn on P-channel BATFET,
connecting the battery to the system.
Asymmetrical gate drive (fast turnoff and slow turnon) for the ACDRV and BATDRV drivers provides fast turn-off
and slow turn-on of the ACFET and BATFET to help the break-before-make logic and to allow a soft-start at
turnon of either FET. The soft-start time can be further increased by putting a capacitor from the gate to the
source of the P-channel power MOSFETs.
8.3.9 Automatic Internal Soft-Start Charger Current
The charger automatically soft-starts the charger regulation current every time the charger goes into fast charge
to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists
of stepping up the charge regulation current in eight evenly divided steps up to the programmed charge current.
Each step lasts around 1.6 ms, for a typical rise time of 12.8 ms. No external components are needed for this
function.
8.3.10 Converter Operation
The synchronous buck PWM converter uses a fixed-frequency voltage mode with a feed-forward control scheme.
A type-III compensation network allows using ceramic capacitors at the output of the converter. The
compensation input stage is connected internally between the feedback output (FBO) and the error amplifier
input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error
amplifier output (EAO). The LC output filter is selected to give a resonant frequency of 12 kHz–17 kHz for the
bq24618, where the resonant frequency, f_o, is given by:
1
f_o =
2p L_o C_o
(7)
An internal sawtooth ramp is compared to the internal EAO error control signal to vary the duty cycle of the
converter. The ramp height is 7% of the input adapter voltage, making it always directly proportional to the input
adapter voltage. This cancels out any loop gain variation due to a change in input voltage and simplifies the loop
compensation. The ramp is offset by 300 mV in order to allow zero-percent duty cycle when the EAO signal is
below the ramp. The EAO signal is also allowed to exceed the sawtooth ramp signal in order to get a 100% duty-
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