TMS320DM6467CCUTA Datasheet, PDF (321/355 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
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SPRS403H – DECEMBER 2007 – REVISED JUNE 2012
Table 7-119. Additional Input Timing Requirements of 5-Pin Option in Master Mode⁽¹⁾
NO.
MIN
21 t_d(CSL-ENA)
Delay time, max delay for slave
SPI to drive SPI_ENA valid after
master asserts SPI_CS[n] to
delay the master from beginning
the next transfer
Delay time, max delay for slave
to deassert SPI_ENA after final
SPI_CLK falling edge, 5-pin
mode, polarity = 0, phase = 0
Delay time, max delay for slave
to deassert SPI_ENA after final
SPI_CLK falling edge, 5-pin
31
t_d(CLK-ENA) ^{(2) (3)}
mode, polarity = 0, phase = 1
Delay time, max delay for slave
to deassert SPI_ENA after final
SPI_CLK rising edge, 5-pin
mode, polarity = 1, phase = 0
Delay time, max delay for slave
to deassert SPI_ENA after final
SPI_CLK rising edge, 5-pin
mode, polarity = 1, phase = 1
(1) T = period of SPI_CLK; P = period of SPI core clock; D = period of 24-MHz clock
(2) SPI master is ready with new data before SPI_ENA deassertion.
(3) Figure 7-87 shows only polarity = 0, phase = 0 as an example.
MAX
0.5P
0.5T
0
0.5T
0
MIN
MAX
UNIT
0.5D ns
0.5T
0
ns
0.5T
0
Slave Mode — Additional
Table 7-120. Additional Output Switching Characteristics of 4-Pin Enable Option in Slave Mode⁽¹⁾
NO.
SPI24 t_d(CLK-EN) ⁽²⁾
PARAMETER
Delay time, final SPI_CLK falling edge to
slave deasserting SPI_EN, polarity = 0,
phase = 0
Delay time, final SPI_CLK falling edge to
slave deasserting SPI_EN, polarity = 0,
phase = 1
Delay time, final SPI_CLK rising edge to slave
deasserting SPI_EN, polarity = 1,
phase = 0
Delay time, final SPI_CLK rising edge to slave
deasserting SPI_EN, polarity = 1,
phase = 1
MIN
P–6
0.5T + P – 6
P–6
0.5T + P – 6
MAX UNIT
3P + 15
0.5T + 3P + 15
ns
3P + 15
0.5T + 3P + 15
(1) T = period of SPI_CLK; P = period of SPI core clock
(2) Figure 7-88 shows only polarity = 0, phase = 0 as an example.
Table 7-121. Additional Output Switching Characteristics of 4-Pin Chip-Select Option in Slave Mode⁽¹⁾
NO.
27
28
t_d(CSL-SOMI)
t_{dis(CSH-SOMI)}
PARAMETER
Delay time, master asserting SPI_CS[n] to slave driving SPI_SOMI
data valid
Disable time, master deasserting SPI_CS[n] to slave driving
SPI_SOMI high impedance
MIN
MAX UNIT
P + 6 ns
P + 6 ns
(1) T = period of SPI_CLK; P = period of SPI core clock
Copyright © 2007–2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 321
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