TMS320DM6467CCUTA Datasheet, PDF (158/355 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
SPRS403H – DECEMBER 2007 – REVISED JUNE 2012
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7.5.2 PLL Controller Register Description(s)
A summary of the PLL controller registers is shown in Table 7-12. For more details, see the
TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number SPRUEP9).
HEX ADDRESS RANGE
0x01C4 0800
0x01C4 08E4
0x01C4 0900
0x01C4 0910
0x01C4 0918
0x01C4 091C
0x01C4 0920
0x01C4 0928
0x01C4 092C
0x01C4 0938
0x01C4 093C
0x01C4 0940
0x01C4 0944
0x01C4 0948
0x01C4 094C
0x01C4 0950
0x01C4 0960
0x01C4 0964
0x01C4 0968
0x01C4 096C
0x01C4 0970
0x01C4 0974
0x01C4 0C00
0x01C4 0D00
0x01C4 0D10
0x01C4 0D18
0x01C4 0D28
0x01C4 0D38
0x01C4 0D3C
0x01C4 0D40
0x01C4 0D44
0x01C4 0D48
0x01C4 0D4C
0x01C4 0D50
0x01C4 0D54 - 0x01C4 0FFF
Table 7-12. PLL and Reset Controller Registers
ACRONYM
PID
RSTYPE
PLLCTL
PLLM
PLLDIV1
PLLDIV2
PLLDIV3
–
BPDIV
PLLCMD
PLLSTAT
ALNCTL
DCHANGE
CKEN
CKSTAT
SYSTAT
PLLDIV4
PLLDIV5
PLLDIV6
–
PLLDIV8
PLLDIV9
PID
PLLCTL
PLLM
PLLDIV1
–
PLLCMD
PLLSTAT
ALNCTL
DCHANGE
CKEN
CKSTAT
SYSTAT
–
REGISTER NAME
PLL1 Controller Registers
Peripheral ID Register
Reset Type Register
PLL Controller 1 PLL Control Register
PLL Controller 1 PLL Multiplier Control Register
PLL Controller 1 Divider 1 Register (SYSCLK1)
PLL Controller 1 Divider 2 Register (SYSCLK2)
PLL Controller 1 Divider 3 Register (SYSCLK3)
Reserved
PLL Controller 1 Bypass Control-Divider Register (SYSCLKBP)
PLL Controller 1 Command Register
PLL Controller 1 Status Register (Shows PLLC1 PLLCTL Status)
PLL Controller 1 Clock Align Control Register
(Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation)
PLL Controller 1 PLLDIV Divider Ratio Change Status Register
(Indicates if SYSCLK Divide Ratio has been modified)
PLL Controller 1 Clock Enable Control Register
PLL Controller 1 Clock Status Register (For All Clocks Except SYSCLKx)
PLL Controller 1 SYSCLK Status Register (Indicates SYSCLK on/off Status)
PLL Controller 1 Divider 4 Register (SYSCLK4)
PLL Controller 1 Divider 5 Register (SYSCLK5)
PLL Controller 1 Divider 6 Register (SYSCLK6)
Reserved
PLL Controller 1 Divider 8 Register (SYSCLK8)
PLL Controller 1 Divider 9 Register (SYSCLK9)
PLL2 Controller Registers
Peripheral ID Register
PLL Controller 2 PLL Control Register
PLL Controller 2 PLL Multiplier Control Register
PLL Controller 2 Divider 1 Register (PLL2_SYSCLK1 DDR2 PHY)
Reserved
PLL Controller 2 Command Register
PLL Controller 2 Status Register (Shows PLLC2 PLLCTL Status)
PLL Controller 2 Clock Align Control Register
(Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation)
PLL Controller 2 PLLDIV Divider Ratio Change Status Register
(Indicates if SYSCLK Divide Ratio has been modified)
PLL Controller 2 Clock Enable Control Register
PLL Controller 2 Clock Status Register (For All Clocks Except SYSCLKx)
PLL Controller 2 SYSCLK Status Register (Indicates SYSCLK on/off Status)
Reserved
158 Peripheral Information and Electrical Specifications
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