TMS320DM6467CCUTA Datasheet, PDF (211/355 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
www.ti.com
SPRS403H – DECEMBER 2007 – REVISED JUNE 2012
Complete stack up specifications are provided in Table 7-35.
DM646x
DDR2
DDR_D0
T
DQ0
DDR_D7
DDR_DQM0 T
DDR_DQS0
DDR_DQS0
DDR_D8
DDR_D15
DDR_DQM1 T
DDR_DQS1
DDR_DQS1
DDR_DQGATE0 T
DDR_DQGATE1
DDR_DQGATE2 ^T
DDR_DQGATE3
DDR_ODT0 NC
DDR_D16
DDR2
ODT
T
DQ0
T
DQ7
LDM
T
LDQS
T
LDQS
T
DQ8
T
DQ15
UDM
T
UDQS
T
UDQS
ODT
DDR_D23
DDR_DQM2 T
DDR_DQS2
DDR_DQS2
DDR_D24
T
DQ7
LDM
T
LDQS
T
LDQS
T
DQ8
DDR_D31
DDR_DQM3 T
DDR_DQS3
DDR_DQS3
DDR_BA0 T
T
DQ15
UDM
T
UDQS
T
UDQS
BA0
BA0
DDR_BA2 T
DDR_A0 T
BA2
A0
BA2
A0
DDR_A14
DDR_CS
DDR_CAS
DDR_RAS
DDR_WE
DDR_CKE
DDR_CLK
DDR_CLK
DDR_VREF
T
T
T
T
T
T
T
T
0.1 µF^(B)
DDR_ZN
DDR_ZP
50 Ω (±5%)
50 Ω (±5%)
A14
CS
CAS
RAS
WE
CKE
CK
CK
VREF
VREF
0.1 µF^(B)
DV_DDR2
A14
CS
CAS
RAS
WE
CKE
CK
CK
VREF
VREF
0.1 µF
0.1 µF^(B)
0.1 µF
T _{Terminator, if desired. See terminator comments.}
A Vio1.8 is the power supply for the DDR2 memories and DM646x DDR2 interface.
B One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin.
Figure 7-27. DM6467 32-Bit DDR2 High Level Schematic
Vio 1.8^(A)
1 K Ω 1%
VREF
1 K Ω 1%
Copyright © 2007–2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 211
Submit Documentation Feedback
Product Folder Link(s): TMS320DM6467