TMS320DM6467CCUTA Datasheet, PDF (288/355 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
SPRS403H – DECEMBER 2007 – REVISED JUNE 2012
www.ti.com
NO.
14 t_FS
15 t_LI
16 t_MLI
17 t_UI
18 t_AZ
19 t_ZAH
20 t_ZAD
21 t_ENV
22 t_RFS
23 t_RP
24 t_IORDYZ
25 t_ZIORDY
26 t_ACK
27 t_SS
Table 7-93. Timings for ATA Module — Ultra DMA AC Timing^{(1) (2)}
(see Figure 7-67 through Figure 7-76) (continued)
First STROBE time
Limited interlock time
Interlock time with minimum
Unlimited interlock time
Maximum time allowed for output drivers to
release
Minimum delay time required for output
Minimum delay time for driver to assert or negate
(from released)
Envelope time, DMACK to STOP and DMACK to
HDMARDY during in-burst initiation and from
DMACK to STOP during data out burst initiation
Ready-to-final-STROBE time
Ready to pause time, (HDMARDY (DIOR) to
STOP (DIOW))
Ready to pause time, (DDMARDY (IORDY) to
DMARQ)
Maximum time before releasing IORDY
Minimum time before driving IORDY
Setup and hold time for DMACK (before
assertion or negation)
STROBE edge to negation of DMARQ or
assertion of STOP (when sender terminates a
burst)
MODE
0
1
2
3
4
5
0-2
3-4
5
0-5
0-5
0-5
0-5
0-5
0-5
0
1
2-4
5
0-5
0
1
2-4
5
0-5
0-5
0-5
0-5
-594, -729
MIN
0
0
0
20
0
20
0
(TENV + 1)P - 0.5
(UDMATRP + 1)P - 0.8
160
125
100
85
0
20
50
MAX
230
200
170
130
120
90
150
100
75
10
(TENV + 1)P + 1.4
75
70
60
50
20
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
288 Peripheral Information and Electrical Specifications
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