TMS320DM6467CCUTA Datasheet, PDF (281/355 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
www.ti.com
SPRS403H – DECEMBER 2007 – REVISED JUNE 2012
7.20 ATA Controller
The ATA peripheral supports the following features:
• PIO, multiword DMA, and Ultra ATA 33/66/100
• Up to mode 4 timings on PIO mode
• Up to mode 2 timings on multiword DMA
• Up to mode 5 timings on Ultra ATA
• Programmable timing parameters
• Supports TrueIDE mode for Compact Flash
7.20.1 ATA Bus Master Memory Map
The ATA Controller supports multiword DMA transfers between external IDE/ATAPI devices and a system
memory bus interface. Table 7-89 shows the memory map for the ATA DMA engine.
Table 7-89. ATA DMA Master Memory Map
START ADDRESS
0x0000 0000
0x1000 0000
0x1001 0000
0x1001 4000
0x1001 8000
0x1002 0000
0x1100 0000
0x1140 0000
0x1150 0000
0x1160 0000
0x1170 0000
0x1180 0000
0x1181 0000
0x1181 8000
0x1183 8000
0x1190 0000
0x11E0 0000
0x11E0 8000
0x11F0 0000
0x11F0 8000
0x1200 0000
0x4C00 0000
0x5000 0000
0x8000 0000
0xA000 0000
0xC000 0000
END ADDRESS
0x0FFF FFFF
0x1000 FFFF
0x1001 3FFF
0x1001 7FFF
0x1001 FFFF
0x10FF FFFF
0x113F FFFF
0x114F FFFF
0x115F FFFF
0x116F FFFF
0x117F FFFF
0x1180 FFFF
0x1181 7FFF
0x1183 7FFF
0x118F FFFF
0x11DF FFFF
0x11E0 7FFF
0x11EF FFFF
0x11F0 7FFF
0x11FF FFFF
0x4BFF FFFF
0x4FFF FFFF
0x7FFF FFFF
0x9FFF FFFF
0xBFFF FFFF
0xFFFF FFFF
SIZE
(BYTES)
256M
64K
16K
16K
32K
16256K
4M
1M
1M
1M
1M
64K
32K
128K
800K
5M
32K
992K
32K
992K
928M
64M
768M
512M
512M
1G
ATA DMA ACCESS
Reserved
Reserved
ARM RAM 0 (Data)
ARM RAM 1 (Data)
ARM ROM (Data)
Reserved
C64x+ L2 RAM/Cache
Reserved
C64x+ L1P RAM/Cache
Reserved
C64x+ L1D RAM/Cache
Reserved
VLYNQ (Remote Data)
Reserved
DDR2 Memory Controller
Reserved
Reserved
Copyright © 2007–2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 281
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