TMS320DM6467CCUTA Datasheet, PDF (140/355 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
SPRS403H – DECEMBER 2007 – REVISED JUNE 2012
www.ti.com
6.2 Recommended Operating Conditions
CV_DD
DV_DD
V_SS
DDR_VREF
DDR_ZP
DDR_ZN
V_IH
V_IL
T_c
F_SYSCLK1
NORM
Supply voltage, Core (CV_DD, DEV_CV_DD,
AUX_CV_DD) ⁽¹⁾
SmartReflex
[-594V, -594AV
only]
[see Table 4-39]
Supply voltage, I/O, 3.3V (DV_DD33, USB_V_DDA3P3)
Supply voltage, I/O, 1.8V (DV_DDR2, PLL1V_DD18, PLL2V_DD18,
DEV_DV_DD18, AUX_DV_DD18, USB_V_DD1P8 ⁽²⁾)
Supply ground (V_SS, PLL1V_SS, PLL2V_SS, DEV_V_SS ⁽³⁾, AUX_V_SS
(3)_{, USB_VSSREF)}
DDR2 reference voltage⁽⁴⁾
DDR2 impedance control, connected via 50-Ω (±5% tolerance)
resistor to V_SS
DDR2 impedance control, connected via 50-Ω (±5% tolerance)
resistor to DV_DDR2
High-level input voltage, 3.3 V (except JTAG[TCK], PCI-capable,
and I2C pins)
High-level input voltage, JTAG [TCK]
High-level input voltage, PCI
High-level input voltage, I2C
High-level input voltage, non-DDR I/O, 1.8 V
Low-level input voltage, 3.3 V (except PCI-capable and I2C pins)
Low-level input voltage, PCI
Low-level input voltage, I2C
Low-level input voltage, non-DDR I/O, 1.8 V
Default
Operating case temperature
(A version)
(D version)
DSP Operating Frequency (SYSCLK1)
-594
-729
MIN
1.14
1.14
1.00
3.14
1.71
0
0.49DV_DDR2
2
2.5
0.5DV_DD33
0.7DV_DD33
0.65DV_DD18
NOM
1.2
1.2
1.05
3.3
1.8
0
0.5DV_DDR2
V_SS
DV_DDR2
0
0
-40
-40
20
20
MAX
1.26
1.26
UNIT
V
V
1.1 V
3.46 V
1.89 V
0V
0.51DV_DDR2
V
V
V
0.8
0.3DV_DD33
0.3DV_DD33
0.35DV_DD18
85
105
85
594
729
V
V
V
V
V
V
V
V
V
°C
MHz
MHz
(1) Future variants of TI SoC devices may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance
options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V,
1.1 V, 1.14 V, 1.2 V, 1.26 V with ± 3% tolerances) by implementing simple board changes such as reference resistor values or input pin
configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of TI SoC
devices.
(2) Oscillator 1.8 V power supply (DEV_DV_DD18) can be connected to the same 1.8 V power supply as DV_DDR2.
(3) Oscillator ground (DEV_V_SS and AUX_V_SS) must be kept separate from other grounds and connected directly to the crystal load
capacitor ground.
(4) DDR_VREF is expected to equal 0.5DV_DDR2 of the transmitting device and to track variations in the DV_DDR2.
140 Device Operating Conditions
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