CC2564C Datasheet, PDF (32/52 Pages) Texas Instruments – CC2564C Dual-Mode Bluetooth Controller

CC2564C
SWRS199A – APRIL 2016 – REVISED NOVEMBER 2016
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Between both Frame_Sync signals there are 70 clock cycles (instead of 100). The clock idle period starts
60 clock cycles after the beginning of the frame and lasts 90 – 60 = 30 clock cycles. Thus, the idle period
ends 100 – 90 = 10 clock cycles before the end of the frame. The data transmission must end before the
beginning of the idle period.
Figure 6-12 shows the frame idle timing.
Frame_Sync
Frame period
Data_In
Data_Out
Clock
Frame idle
Clk_Idle_Start
Clk_Idle_End
Figure 6-12. Frame Idle Period
frmidle_swrs064
6.4.3.5 Clock-Edge Operation
The codec interface of the device can work on the rising or the falling edge of the clock and can sample
the Frame_Sync signal and the data at inversed polarity.
Figure 6-13 shows the operation of a falling-edge-clock type of codec. The codec is the master of the bus.
The Frame_Sync signal is updated (by the codec) on the falling edge of the clock and is therefore
sampled (by the device) on the next rising clock. The data from the codec is sampled (by the device) on
the falling edge of the clock.
PCM FSYNC
PCM CLK
PCM DATA IN
D7 D6 D5 D4 D3 D2 D1 D0
CC256x
SAMPLE TIME
SWRS121-004
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Figure 6-13. Negative Clock Edge Operation
6.4.3.6 Two-Channel Bus Example
Figure 6-14 shows a 2-channel bus in which the two channels have different word sizes and arbitrary
positions in the bus frame.
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